02-Creating-act- HDL Graphical Modules (1274893), страница 3
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The timebetween transitions is expressedas: Integer multiple of a synchronizationsignal (Clock) cycle in case ofsynchronous state machinesInteger multiple of a value specified inthe Delay propagation case ofasynchronous state machineswww.aldec.com55State register port• Contents of the state register can be passed to a combinatorialoutput vector.
This is useful when creating Full Moore machinesand for debugging purposes as well.www.aldec.com56Synthesis attributes• Synthesis attributes can be••added to the generated HDLcode for better control andimprovementofFSMsynthesis results.Enable Synthesis Attributesand choose the tool youwould like to use forsynthesis in Code GenerationSettingsSelect the appropriate valuesfor attributes supported byyour synthesis tool.www.aldec.com57Export to previous ASF format• As•new featureswere introduced inthe Finite StateMachine Editor, fileformatshadtoevolve.Forbackwardscompatibility,theFSM Editor providesExport to old fileformatsoptionavailable in Filemenu.www.aldec.com58Report file generation• The State Diagram Editor••generates documentationfor the state machine.The ASF Report is anauxiliary tool that gatherscomplete information aboutthe created state machine.It contains details of porttypes, structure of thedesignhierarchytree,specified reset signal(s) andactive clock's edge, headers,etc.www.aldec.com.
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