суперкомпьютер семейства ILLIAC (ILLInois Automated Computer)

The ILLlAC IV System represents a fundamentally different approach t odata processing. The limitation imposed by the velocity of light, oncethought to be an absolute upper bound on computing power, has beenstepped over by several approaches to computer architecture, of which theILLIAC IV is the most powerful by as much as a factor of four.The conquest of the limitations of the velocity of light was foreseen byHerman Kahn and A.J. Wiener in 1967,when they wrote: ".

. . . .over thepast fifteen years this basic criterion of computer performance hasincreased by a factor of ten every two or three years . . . . . While some willargue that we are beginning to reach limits set by basic physical constants,such as the speed of light, this may not be true, especially when oneconsiders new techniques in time sharing, segmentation of programs to addflexibility, and parallel processing computers. . .(such as).

. .the ILLIAC IV#I. a .ILLIAC IV represents a significant step forward in computer systemsarchitecture offering- greatly improved performances:200 MIPS computation speed109 bitslsec I10 transfer rate106 bytes of high-speed integrated circuit memories2.5 X 109bits of parallel disk storage- contemporary technology:ECL circuitssemiconductor memoriesbelted cables- and a new approach to the artIL LIAC 1V Quadrantof computing using parallelism,which offers an opportunity t o programmers to utilize the vastpower of the system as effectively as possible.MAJOR SYSTEM ELEMENTSAs shown in the accompanying system diagram, the major elements of theILLIAC IV System are the Array Subsystem, the I10 Subsystem, the DiskFile Subsystem, and the B 6700 Control Computer Subsystem.AThe main computing power resides in the Array Subsystem.

The ECLcircuit family is used to implement the logic in the Array Subsystem. In thearray is a Control Unit (CU) directly governing 64 identical Processing Units(PU). Each PU is principally a combination of a Processing Element (PE)and a Processing Element Memory (PEM). The PE has no independentcontrol except for mode, some data dependent conditions, and addressingwithin i t s own memory. Mode control permits a PE to accept or ignore abroadcast control sequence from the CU, depending on the current statusof i t s mode bit.

The PE is essentially a four-register arithmetic unit capableof executing a full repertoire of instructions having 64-bit, 32-bit, and &bitoperands. Directly associated with each PE is a PEM having 2048 words of64-bits each, 4096 words of 32 bits each, or some combination of bothsizes.ARRAYSUBSYSTEMICONTROL UNITThe 110 Subsystem controls the routing of data among the other majorelements of the system a?d a 1024-bit wide interface that may be used for avariety of purposes, depending on the application.The Disk F'ile Subsystem provides an intermediate data storage for the arrayhaving a storage capacity up to 2.5 X lo9 bits of storage and a transfer rateup to lo9 bits per second.A B 6700 is the control computer for the ILLIAC IV System.

Thiscomputer provides executive control, facility allocation, peripheralequipment control, 110 initiation and control, fault recovery, and programassembly and compilation.The logic of the I10 Subsystem, the Disk File Subsystem, and the B 6700Control Computer Subsystem is implemented in the CTL circuit family.Each of these elements of the system is discussed in more detail on thefollowing pages.L --,--,,,,J,lL LlAC I V Functional DiagramFEATU.RES OF ARRAY OPERATIONEfficient operation of parallel array programs requires machine featuresthat are unfamiliar to designers and users of conventional serialmachines. The following discussion, which highlights the operation of thearray at the individual instruction level, has several sections.

The firstpresents the conventional aspects of array operation, and hence, discusseswhat appears to be a conventional instruction set. The other sectionsdiscuss the capabilities which have been added to facilitate array processing,such as on-off control of the Processing Elements, routing of data among.Processing Elements, one-clock alignment and normalization of floatingpoint numbers, independence among PE's of the address field of theinstruction, and broadcasting.CONVENTIONAL INSTRUCTION SETThere are 65 computers in the ILLIAC IV array.

Of these, 64 are identical,and are called the Processing Elements (PE). The 65th computer isimbedded in the Control Unit (CU). Most instructions are conventional,such as add, multiply, fetch, store, and are either PE or CU instructions. APE multiply instruction, for example, causes the contents of every PEaccumulator to be multiplied by a second operand specified in the addressfield of the instruction. A CU add instruction adds the contents of one ofthe words of the local operand store to the contents of one of the fouraccumulators in the CU. The CU computer is used for purposes like loopcontrol. The major burden of the data processing is on the PE's, whoseinstruction set is relatively conventional, containing instructions such asadd, multiply, logical OR, divide, fetch, store, and register-to-registermoves.

Typical instruction times are given on page 8.until all PE's had reported the completion of shifting. The 240-nanosecondperiod is the round trip time for the cabinet length of over 50 feet.A barrel switch is, therefore, provided in the PE that can shift any amountin one-clock time. The CU, giving the command to normalize, does notwait for a response before going on. Likewise, all shift instructions takeone clock time since they use the same barrel switch.ROUTINGRouting is a mechanism whereby the PE's can exchange data rapidly andsimultaneously.

The instruction that accomplishes this is called the "route"instruction. Routing consists of taking 64 words of data in the 64 registersin the 64 PE's and shifting it among the PE's by distance N modulo64. That is, data starting in PEo winds up in PEN; data starting in PE1winds up in PEN+^. All such shifts are done simultaneously, so that all 64words of data are transferred in one shift time. Shift time is a function ofN, being the minimum of 125 nanoseconds for distances of either 1,8, -1,or -8.ONE CLOCK NORMALIZATIONAll PE's must operate together with essentially no control response back tothe CU. For example, when normalizing sums from floating point addition,every PE has a different shift amount.

If the various PE's took differenttimes to shift, the CU would have to wait a minimum of 240 nanosecondsThe above figure shows this end-around routing connectionschematically. In addition to the neighbor-to neighbor linkages which formthe PE's into a ring, there are connections of PE's eight apart such that datacan leapfrog intermediate PE's when the distance to be covered is large.ON-OFF CQNTROLOn-off control of the PE is effected with control bits called modebits. When the mode bit is set, the PE is operating normally; when themode bit is reset, the PE will not execute the current instruction.

Resettingthe mode bit is, therefore, a mechanism whereby the PE can branchforward in the instruction stream.There are two ways of controlling the PE's with the mode bits. Mode bitsmay be set by the result of tests in the PE's, or they may be setunconditionally by the CU. To illustrate the first method, assume a casewhere the PE should control its own performance (Let P be the PEnumber):IF X(P) >Y(P) THEN DO STATEMENT A,ELSE DO STATEMENT B.In the lLLlAC IV, the code would read as follows, and 64 passes throughthe code would be executed simultaneously.If X(P) >Y(P) set mode bit (P) to ON; Statement A; Complement mode bits; Statement B; Set all mode bits on; Next statement; In the extended FORTRAN being implemented for ILLIAC IV, PE's can beturned on and off by "control vectors." These vectors have one bit perelement, and are used to mask out any given operation.

The control vectorsare fetched to the CU and sent directly to the mode bits of each PE.In conventional computers the code would read something like thefollowing:LMIf X(P) >Y(P) then go to L;Statement B;Go to M;Statement A;Next. statement;Since the PE's each can operate on either one 64-bit word or two 32-bitwords, two separate mode bits are provided in each PE for 32-bit operationso that control vectors or PE tests can turn on and off the halves of the PEindependently of each other. The effect, as far as mode bits are concerned,is like having 128 independent 32-bit Processing Elements. Mode bitcontrol does not interfere with routing.IINDEPENDENCE OF ADDRESSING AMONG PE MEMORIESmAlthough each PE instruckion is for 64 PE's, it contains only one addressfield.