суперкомпьютер семейства ILLIAC (ILLInois Automated Computer), страница 4

In addition, the CUmonitors and controls the status of the PE's by using one input and oneoutput of the mode logic in each PE. Similarly, it monitors the memoryprotect status of the PEM's by using an output from each MLU.Processing UnitProcessing ElementThe PE is the execution portion of the PU and is devoid of all independentcontrol with the exception of mode, which may be set by some datadependent conditions.

Mode control permits a PE to accept or ignore abroadcast control sequence from the CU, dependent on i t s currentstatus. The PE is essentially a four-register arithmetic unit, as shown in thefigure, capable of executing a full repertoire of instructions having 64-bit,32-bit, or 8-bit operands. Further, operations involving 64-bit and 32-bitwords can be done in either fixed-point or floating-point representation.An arithmetic unit in the PE combines a carry-save adder tree and paralleladder with carry look-ahead logic to give a floating-point multiply in 9clocks and a floating-point add in 5 clocks. Both times includepost-normalization.The instruction set of the PE is that of a largescale, general-purposedigitalcomputer. Floating point arithmetic in both 64-bit and 32-bit words isprovided, with options for rounding and normalization. Full wordoperations, 8-bit byte operations, operations ignoring exponents, operationsusing exponents only, and operations ignoring the4gns are among theinstructions provided in the arithmetic group.

A full set of tests is generatedb y making all registers addressable and providing all possiblecomparisons. Test results are set into a mode bit which may be used toI." .,direct the flow of the instruction execution. Bit manipulation, shifts andlogical operations are also included in the instructions set...-m, . ..""L"".,."ELEMENTSProcessing Element MemoryM REGISTER(ADDRESS)The PEM provides the high speed, random access, primary storage for theILLlAC IV. Each PEM provides storage for 2048 64-bit words, which totals131,072words.

To obtain the high speed necessary for array operation, thePEM has been implemented using semiconductor memory techniques. ThePEM interfaces with, and is directly controlled by, the MLU.ADDRESS ADDER YX REGISTERINDEXThe first 128 words of each PEM can be write-protected by setting anappropriate control bit. If a write is attempted in any of the word locations0 through 127 when the bit is set, the memory cycle will not occur.Memory Logic UnitThe MLU controls and effects the transfer of data between the PEM, theCU, the PE, and the 110 Subsystem.

The MLU also enables non-memorydata transfers between the CU and the PE. In addition to the timing andcontrol logic for PEM operations, the MLU contains a memory informationregister used for the temporary storage of data to be written into or readfrom the PEM.DISK Fl LE SUBSYSTEM,ADDRESSTO PEPEM DATA-- -Processing ElementdThe ILLIAC IV Disk File Subsystem is based upon Burroughs' continuingdevelopment in head-per-track disk files.

In each Storage Unit (SU),containing one independently rotating disk, 128 of these heads aresimultaneously written or read, to achieve a data rate of 502 X lo6 bits persecond. Capacity is 78,643,200bits of data storage per Storage Unit. Thedisk in each Storage Unit rotates at 1530 rpm, for a rotation period of 39.2ms, and an average access time of 19.6 ms for a single item. For multipleitems, the Optimizer contained within the I10 Subsystem is capable of up toTWO data paths exist between the B 6700 Subsystem and the I/OSubsystem, one path being the Buffer I/O Memory (BIOM), and the otherpath leading directly into the Descriptor Controller (DC).

The BlOMfunctions as a module of B 6700 memory, as seen from the B 6700,handling data transfers from the B 6700 into the I/O Subsystem. As seenfrom the ILLIAC IV system diagram on the next page, the BlOM cantransfer data either onto the disk file or directly into the arraymemory.

The data path t o the DC uses the 48-bit word interface of theB 6700 multiplexor, which allows the DC to share a memory bus with themultiplexor;9The DFC consists of two controllers that execute descriptors held in the DCfor transfers between disk and array, disk and BIOM, BlOM and array, andreal-time link and array. All transfers involving the array are via the IOS.Disk File Subsystem24 separate disk accesses within the 39.2 ms period. Upto 16 Storage Unitsare serviced by a single Electronics Unit (EU). The ILLIAC IV System isdesigned to accept two EU's, for a combined storage capacity of2,516,582,400 bits and a transfer of 1.004 billion bits per second. Each ofthe 128 tracks is split into three data lines, at one third the data rate, forinterface to the Disk File Controller (DFC), so that there are 384.

data linesbetween the EU and DFC. When the EU is not busy, these same lines areused to continually transmit the present rotational position (address) of allsixteen storage disks to the Optimizer.The IOS buffers and distributes data between the DFC and the ILLlAC IVarray. The IOS has a 256-bit bidirectional interface with each of the twoDFC units and a 1024-bit bidirectional interface with the ILLIAC IVarray. The IOS also provides a 1024-bit wide external data link to the array.The DC receives control words over the scan bus interface and fetches I/Odescriptors over the multiplexor word interface in response to these controlwords. The DC sends result descriptors over the scan bus upon thecompletion of 110 transactions. Certain I10 descriptors cause the DC tosend words of data, fetched over the multiplexor word interface, to the CU,where they are treated as instructions by the TMU.

There is a 48-bitbidirectional interface between DC and TMU for these transfers.I10 SUBSYSTEMThe I10 Subsystem, shown in the system diagram on the right, consists ofthe Descriptor Controller (DC), I/O Switch (IOS), Buffer I10 Memory(BIOM), and Disk File Controllers (DFC).The interface between the I/O Subsystem and the B 6700 control computeris designed to take advantage of the existing properties of the B 6700, whilekeeping simple the interface to the ILLIAC IV array.

Control words arereceived over the scan bus interface provided from the B 6700 processor,and results are described in words transmitted back over this same interface.B 6700 CONTROL COMPUTER SUBSYSTEMThe primary functions of the B 6700 control computer are to execute thesupervisory program and prepare programs for the ILLIAC IV byassembling, compiling, etc. The supervisory program schedules jobs for thearray; maintains the parallel disk files; transmits control records(descriptors) to the 110 Subsystem, which directs the I10 transactions inand out of the array; responds to interrupt conditions from the array andelsewhere; and communicates with the user and operator.As a secondary function, the B 6700 has associated with it a full range ofperipheral equipments.

Consequently, the B 6700 provides the ILLIAC IVsystem with such peripheral capabilities as may be needed. On-line datacommunication may be added to the system by including a DataCommunication Processor and line adapters.! 'Data CommunicationsBecause the B 6700 is designed for multiprocessing, the system readilyaccommodates applications and procedures requiring datacommunications. The B 6350 Data Communications Processor (DCP) is theheart of the data communications network.

It is a small, special-purposecomputer containing the registers, logic, and translation ability to performall the basic functions associated with sending and receiving data. Up to 8DCP's can be connected to a B 6700 and each can handle up to 256communications lines. Adapters are available to handle line speeds up to9600 baud,Touch-Ton&, Audio Response, and Automatic Dial Out.

Thenumber of lines mat can be serviced by a DCP varies as a function of linespeed, loading, and discipline as well as the terminal mix and theapplication.B 6700 CONTROL COMPUTER SUBSYSTEMPROCESSORLJARPA INTERFACEADAPTERAn interface with the ARPA Network has been developed for users needingthis type of data communication, and will be installed on the initial ILLlACIV at Ames Laboratories.I6~egisteredtrademark of the AT & T Co. -IELECTRONICsI384ICDlSK FlLEONTR(DFC-1)IIIIDlSK FILE SUBSYSTEML,,,,,,,~II--INPUTOUTPUTSWITCH(10s)1024INTERFACE1/0 SUBSYSTEM11I1PEPE123II1IIPEMPEMPEMIIIIIIILLIAC I VSYSTEM DIAGRAM.ARRAY SUBSYSTEMIII256CONTROLUNITPEI128 DlSK FlLECONTROLLER N0.2(DFC-2)III~256I1384 J128DESCRIPTORCONTROLLER(DC)1..aPE641 '.a.PEMINOTEThe numbers show how many data b m aretransm~ttedin parallel on any glven data path.DATA FLOW hardware address. The Optimizer controls will allow the MCP to puttogether as many as 15 disk file a&lresses into a single package, which,barring conflicts, will all be read during a single disk revolution of 40 ms.-.- y 3 3.;88-, 7 - 3 -The history of one program being executed in the ILLIAC IV can betracked by tracing the sequential steps in the flow of data during theexecution of a job from the gleam in the operator's eye to the productionof the final printout.

The steps in the data path are as follows.Data enters the system from the peripherals of the B 6700, initially. I f thedata for this job is the result of output from a previous task, the data maybe found in a bulk store. This data will be moved from the external source,whatever it is, to the parallel disk file before the job is executed.For data coming from the bulk store, the data path is to the BIOM and thento the ILLIAC disk (Path 1B in the figure). For data brought in fromperipheral devices, the path is shown as "IA" through the multiplexor inthe figure. The B 6700 MCP controls this path. A t the programmer'soption, the B 6700 may perform formatting or preprocessing of the data onentrance.