Микроконтроллер Motorola 68HC11, страница 9

A wait state is entered which remains in effect for an integer number of MPU E-Clockcycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).Operandsdd= 8-Bit Direct Address ($0000 –$00FF) (High Byte Assumed to be $00)ff= 8-Bit Positive Offset $00 (0) to $FF (255) (Is Added to Index)hh= High-Order Byte of 16-Bit Extended Addressii= One Byte of Immediate Datajj= High-Order Byte of 16-Bit Immediate Datakk= Low-Order Byte of 16-Bit Immediate Datall= Low-Order Byte of 16-Bit Extended Addressmm= 8-Bit Mask (Set Bits to be Affected)rr= Signed Relative Offset $80 (–128) to $7F (+127)(Offset Relative to Address Following Machine Code Offset Byte))3Operators()Contents of register shown inside parentheses⇐Is transferred to⇑Is pulled from stack⇓Is pushed onto stack•Boolean AND+Arithmetic Addition Symbol except where used as Inclusive-OR symbolin Boolean Formula⊕Exclusive-OR∗Multiply:Concatenation–Arithmetic subtraction symbol or Negation symbol (Two’s Complement)MOTOROLA3-14Condition Codes—Bit not changed0Bit always cleared1Bit always set∆Bit cleared or set, depending on operation↓Bit can be cleared, cannot become setCENTRAL PROCESSING UNITM68HC11 E SERIESTECHNICAL DATASECTION 4 OPERATING MODES AND ON-CHIP MEMORYThis section contains information about the operating modes and the on-chip memoryfor M68HC11 E-series MCUs.

Except for a few minor differences, operation is identicalfor all devices in the E series. Differences are noted where necessary.4.1 Operating ModesThe values of the mode select inputs MODB and MODA during reset determine theoperating mode. Single-chip and expanded multiplexed are the normal modes. In single-chip mode only on-chip memory is available. Expanded mode, however, allows access to external memory. Each of the two normal modes is paired with a special mode.Bootstrap, a variation of the single-chip mode, is a special mode that executes a bootloader program in an internal bootstrap ROM.

Test is a special mode that allows privileged access to internal resources.4.1.1 Single-Chip ModeIn single-chip mode, ports B and C and strobe pins A (STRA) and B (STRB) are available for general-purpose parallel I/O. In this mode, all software needed to control theMCU is contained in internal resources.

ROM/EPROM (if present) will always be enabled out of reset, ensuring that the reset and interrupt vectors will be available at locations $FFC0–$FFFF. For the MC68HC811E2, the vector locations are the same,however, they are contained in the 2048-byte EEPROM array.4.1.2 Expanded ModeIn expanded operating mode, the MCU can access the full 64-Kbyte address space.The space includes the same on-chip memory addresses used for single-chip modeas well as addresses for external peripherals and memory devices.

The expansion busis made up of ports B and C, and control signals AS and R/W. The R/W (read/write)and AS (address strobe) allow the low-order address and the 8-bit data bus to be multiplexed on the same pins. During the first half of each bus cycle address informationis present. During the second half of each bus cycle the pins become the bidirectionaldata bus. AS is an active-high latch enable signal for an external address latch. Address information is allowed through the transparent latch while AS is high and islatched when AS drives low.The address, R/W, and AS signals are active and valid for all bus cycles, including accesses to internal memory locations.

The E clock is used to enable external devicesto drive data onto the internal data bus during the second half of a read bus cycle (Eclock high). R/W controls the direction of data transfers. R/W drives low when data isbeing written to the internal data bus. R/W will remain low during consecutive data buswrite cycles, such as when a double-byte store occurs. Notice that the write enable signal for an external memory is the NAND of the E clock and the inverted R/W signal.Refer to the example diagram of address and data demultiplexing.M68HC11 E SERIESTECHNICAL DATAOPERATING MODES AND ON-CHIP MEMORYMOTOROLA4-14ADDR15ADDR14ADDR13ADDR12ADDR11ADDR10ADDR9ADDR8PB7PB6PB5PB4PB3PB2PB1PB0HC373PC7PC6PC5PC4PC3PC2PC1PC0ASR/WED1D2D3D4D5D6D7D8LEQ1Q2Q3Q4Q5Q6Q7Q8OEADDR7ADDR6ADDR5ADDR4ADDR3ADDR2ADDR1ADDR0WEOE4MCUDATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0ADDR/DATA DEMUXFigure 4-1 Address/Data Demultiplexing4.1.3 Test ModeTest mode, a variation of the expanded mode, is primarily used during Motorola’s internal production testing; however, it is accessible for programming the CONFIG register, programming calibration data into EEPROM, and supporting emulation anddebugging during development.4.1.4 Bootstrap ModeWhen the MCU is reset in special bootstrap mode, a small on-chip ROM is enabled ataddress $BF00–$BFFF.

The ROM contains a bootloader program and a special set ofinterrupt and reset vectors. The MCU fetches the reset vector, then executes the bootloader. Bootstrap mode is a special variation of the single-chip mode. Bootstrap modeallows special-purpose programs to be entered into internal RAM. When boot mode isselected at reset, a small bootstrap ROM becomes present in the memory map. Resetand interrupt vectors are located in this ROM at $BFC0–$BFFF. The bootstrap ROMcontains a small program which initializes the SCI and allows the user to download aprogram into on-chip RAM. The size of the downloaded program can be as large asthe size of the on-chip RAM. After a four-character delay, or after receiving the character for the highest address in RAM, control passes to the loaded program at $0000.Refer to the memory map diagram.Use of an external pull-up resistor is required when using the SCI transmitter pin because port D pins are configured for wired-OR operation by the bootloader.

In bootMOTOROLA4-2OPERATING MODES AND ON-CHIP MEMORYM68HC11 E SERIESTECHNICAL DATAstrap mode, the interrupt vectors are directed to RAM. This allows the use of interruptsthrough a jump table. Refer to Motorola application note AN1060, M68HC11 BootstrapMode.4.2 Memory MapThe operating mode determines memory mapping and whether external addressescan be accessed.

Refer to Figure 4-2, Figure 4-3, and Figure 4-4, which illustrate thememory maps for each of the three families comprising the M68HC11 E series ofMCUs. Memory locations for on-chip resources are the same for both expanded andsingle-chip modes. Control bits in the CONFIG register allow EPROM and EEPROM(if present) to be disabled from the memory map. The RAM is mapped to $0000 afterreset. It can be placed at any 4-Kbyte boundary ($x000) by writing an appropriate value to the INIT register. The 64-byte register block is mapped to $1000 after reset andcan also be placed at any 4-Kbyte boundary ($x000) by writing an appropriate valueto the INIT register.

If RAM and registers are mapped to the same boundary, the first64 bytes of RAM will be inaccessible. Refer to Table 4-1, which details the MCU register and control bit assignments.0000$0000512 BYTES RAMEXTEXT$100001FF1000EXTEXTB600$B60064-BYTE REGISTER BLOCK103F512 BYTES EEPROMB7FFEXTEXTBF00BOOTROMBFFFBFFF$D000D000BFC012 KBYTES ROM/EPROMFFC0FFFF$FFFFSINGLECHIPEXPANDEDBOOTSTRAPSPECIAL MODESINTERRUPTVECTORSFFFFNORMALMODESINTERRUPTVECTORSSPECIALTESTE SERIES MEM MAP P1Figure 4-2 Memory Map for MC68HC11E0, MC68HC11E1, MC68HC11E8,and MC68HC(7)11E9M68HC11 E SERIESTECHNICAL DATAOPERATING MODES AND ON-CHIP MEMORYMOTOROLA4-340000$0000768 BYTES RAMEXTEXT$100002FF1000EXTEXT$9000EXTEXT$B60064-BYTE REGISTER BLOCK103F9000AFFF8 KBYTES ROM/EPROM *B600512 BYTES EEPROMB7FFEXTEXTBF00BOOTROMBFFF$D000BFC0 SPECIAL MODESINTERRUPTBFFF VECTORSD000 12 KBYTES ROM/EPROM *FFC04FFFF$FFFFSINGLECHIPEXPANDEDBOOTSTRAPFFFFNORMALMODESINTERRUPTVECTORSSPECIALTEST* 20 KBYTES ROM/EPROM ARE CONTAINED IN TWO SEGMENTS OF 8 KBYTES AND 12 KBYTES EACH.E SERIES MEM MAP P2Figure 4-3 Memory Map for MC68HC(7)11E20MOTOROLA4-4OPERATING MODES AND ON-CHIP MEMORYM68HC11 E SERIESTECHNICAL DATA$00000000256 BYTES RAMEXTEXT$100000FF100064-BYTE REGISTER BLOCK103FEXTEXTBF00BOOTROMBFFFBFC0 SPECIAL MODESINTERRUPTBFFF VECTORS2048 BYTES EEPROM$F800F800FFFF$FFFFSINGLECHIPEXPANDEDBOOTSTRAPFFC0FFFFNORMALMODESINTERRUPTVECTORSSPECIALTESTE SERIES MEM MAP P3Figure 4-4 Memory Map for MC68HC811E2M68HC11 E SERIESTECHNICAL DATAOPERATING MODES AND ON-CHIP MEMORYMOTOROLA4-54Table 4-1 Register and Control Bit Assignments$1000Bit 7PA76PA6The register block can be remapped to any 4K boundary54321PA5PA4PA3PA2PA1Bit 0PA0$1001Reserved$1002STAFSTAICWOMHNDSOINPLSEGAINVBPIOC$1003PC7PC6PC5PC4PC3PC2PC1PC0PORTC$1004PB7PB6PB5PB4PB3PB2PB1PB0PORTB$1005PCL7PCL6PCL5PCL4PCL3PCL2PCL1PCL0PORTCLReserved$10064PORTA$1007DDC7DDC6DDC5DDC4DDC3DDC2DDC1DDC0$100800PD5PD4PD3PD2PD1PD0$100900DDD5DDD4DDD3DDD2DDD1DDD0DDRD$100APE7PE6PE5PE4PE3PE2PE1PE0PORTE$100BFOC1FOC2FOC3FOC4FOC5000CFORC$100COC1M7OC1M6OC1M5OC1M4OC1M3000OC1M$100DOC1D7OC1D6OC1D5OC1D4OC1D3000OC1D$100EBit 1514131211109Bit 8TCNT (High)$100FBit 7654321Bit 0TCNT (Low)$1010Bit 1514131211109Bit 8TIC1 (High)$1011Bit 7654321Bit 0TIC1 (Low)$1012Bit 1514131211109Bit 8TIC2 (High)$1013Bit 7654321Bit 0TIC2 (Low)$1014Bit 1514131211109Bit 8TIC3 (High)$1015Bit 7654321Bit 0TIC3 (Low)$1016Bit 1514131211109Bit 8TOC1 (High)$1017Bit 7654321Bit 0TOC1 (Low)$1018Bit 1514131211109Bit 8TOC2 (High)MOTOROLA4-6OPERATING MODES AND ON-CHIP MEMORYDDRCPORTDM68HC11 E SERIESTECHNICAL DATATable 4-1 Register and Control Bit Assignments (Continued)$1019Bit 7654321Bit 0TOC2 (Low)$101ABit 1514131211109Bit 8TOC3 (High)$101BBit 7654321Bit 0TOC3 (Low)$101CBit 1514131211109Bit 8TOC4 (High)$101DBit 7654321Bit 0TOC4 (Low)$101EBit 1514131211109Bit 8TI4/O5 (High)$101FBit 7654321Bit 0TI4/O5 (Low)$1020OM2OL2OM3OL3OM4OL4OM5OL5TCTL1$1021EDG4BEDG4AEDG1BEDG1AEDG2BEDG2AEDG3BEDG3ATCTL2$1022OC1IOC2IOC3IOC4II4/O5IIC1IIC2IIC3ITMSK1$1023OC1FOC2FOC3FOC4FI4/O5FIC1FIC2FIC3FTFLG1$1024TOIRTIIPAOVIPAII00PR1PR0TMSK2$1025TOFRTIFPAOVFPAIF0000TFLG2$1026DDRA7PAENPAMODPEDGEDDRA3I4/O5RTR1RTR0PACTL$1027Bit 7654321Bit 0PACNT$1028SPIESPEDWOMMSTRCPOLCPHASPR1SPR0SPCR$1029SPIFWCOL0MODF0000SPSR$102ABit 7654321Bit 0SPDR$102BTCLRSCP21SCP1SCP0RCKBSCR2SCR1SCR0BAUD$102CR8T80MWAKE000SCCR1$102DTIETCIERIEILIETERERWUSBKSCCR2$102ETDRETCRDRFIDLEORNFFE0SCSR$102FR7/T7R6/T6R5/T5R4/T4R3/T3R2/T2R1/T1R0/T0SCDR$1030CCF0SCANMULTCDCCCBCAADCTL$1031Bit 7654321Bit 0ADR1$1032Bit 7654321Bit 0ADR2$1033Bit 7654321Bit 0ADR3M68HC11 E SERIESTECHNICAL DATAOPERATING MODES AND ON-CHIP MEMORYMOTOROLA4-74Table 4-1 Register and Control Bit Assignments (Continued)4$1034Bit 7654321Bit 0$1035000PTCONBPRT3BPRT2BPRT1BPRT0$1036MBE0ELATEXCOLEXROWT1T0PGMADR4BPROTEPROG2$1037Reserved$1038Reserved$1039ADPUCSELIRQEDLYCME0CR1CR0OPTION$103ABit 7654321Bit 0COPRST$103BODDEVENELAT3BYTEROWERASEEELATEPGMPPROG$103CRBOOTSMODMDAIRVNEPSEL3PSEL2PSEL1PSEL0HPRIO$103DRAM3RAM2RAM1RAM0REG3REG2REG1REG0INIT$103ETILOP0OCCRCBYPDISRFCMFCOPTCONTEST1$103FEE34EE24EE14EE04NOSECNOCOPROMONEEONCONFIGNOTES:1.