Микроконтроллер Motorola 68HC11, страница 7

Normally the SP is initialized by one of the first instructions in an application program. The stack is configured as a data structure that grows downward fromhigh memory to low memory. Each time a new byte is pushed onto the stack, the SPis decremented. Each time a byte is pulled from the stack, the SP is incremented. Atany given time, the SP holds the 16-bit address of the next free location in the stack.Figure 3-2 is a summary of SP operations.MOTOROLA3-2CENTRAL PROCESSING UNITM68HC11 E SERIESTECHNICAL DATAJSR, JUMP TO SUBROUTINEWAI, WAIT FOR INTERRUPTMAIN PROGRAMPCDIRECT$9D = JSRddRTN NEXT MAIN INSTR.MAIN PROGRAMPCINDEXED, X$AD = JSRffRTN NEXT MAIN INSTR.MAIN PROGRAMPCINDEXED, Y$18 = PRE$AD = JSRRTNffNEXT MAIN INSTR.7STACKPCSPSP+1SP+2SP+3SP+4SP+5SP+6SP+7SP+8é SP+9INTERRUPT ROUTINE07SP+2SP+3SP+4SP+5SP+6SP+7SP+8é SP+9SWI, SOFTWARE INTERRUPTMAIN PROGRAMPC$3F = SWI7JMP, JUMPSPÐ7SPÐ6SPÐ5WAI, WAIT FOR INTERRUPTSPÐ4MAIN PROGRAMSPÐ3$3E = WAISPÐ2SPÐ1MAIN PROGRAMPC$6E = JMPffSPMAIN PROGRAMPC$8D = BSRINDEXED, Y$18 = PRE$6E = JMPffRTS, RETURN FROMSUBROUTINEMAIN PROGRAM$39 = RTSX + ff NEXT MAIN INSTR.EXTENDED$7E = JMPhhllhh ll NEXT MAIN INSTR.0RTNHRTNL7STACK0SPSP+1é SP+2MAIN PROGRAMSTACKé SPÐ2SPPCPC7SPÐ1MAIN PROGRAMPC3BSR, BRANCH TO SUBROUTINEINDEXED, XX + ff NEXT MAIN INSTR.0CCRACCBACCAIXHIXLIYHIYLRTNHRTNLSPÐ8PCSTACKé SPÐ9MAIN PROGRAMINDEXED, YCCRACCBACCAIXHIXLIYHIYLRTNHRTNLSP+1PC$BD = PREhhRTNllNEXT MAIN INSTR.0SP$3E = WAICCRACCBACCAIXHIXLIYHIYLRTNHRTNLSTACKRTNHRTNLLEGEND:RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TOBE EXECUTED UPON RETURN FROM SUBROUTINERTNH = MOST SIGNIFICANT BYTE OF RETURN ADDRESSRTNL = LEAST SIGNIFICANT BYTE OF RETURN ADDRESSé = STACK POINTER POSITION AFTER OPERATION IS COMPLETEdd = 8-BIT DIRECT ADDRESS ($0000Ð$00FF) (HIGH BYTE ASSUMEDTO BE $00)ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (256) IS ADDED TO INDEXhh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESSll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESSrr= SIGNED RELATIVE OFFSET $80 (Ð128) TO $7F (+127) (OFFSETRELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODEOFFSET BYTE)HC11 STACK OPERATIONSFigure 3-2 Stacking OperationsM68HC11 E SERIESTECHNICAL DATACENTRAL PROCESSING UNITMOTOROLA3-3When a subroutine is called by a jump to subroutine (JSR) or branch to subroutine(BSR) instruction, the address of the instruction after the JSR or BSR is automaticallypushed onto the stack, least significant byte first.

When the subroutine is finished, areturn from subroutine (RTS) instruction is executed. The RTS pulls the previouslystacked return address from the stack, and loads it into the program counter. Execution then continues at this recovered return address.When an interrupt is recognized, the current instruction finishes normally, the returnaddress (the current value in the program counter) is pushed onto the stack, all of theCPU registers are pushed onto the stack, and execution continues at the addressspecified by the vector for the interrupt. At the end of the interrupt service routine, anRTI instruction is executed.

The RTI instruction causes the saved registers to be pulledoff the stack in reverse order. Program execution resumes at the return address.3There are instructions that push and pull the A and B accumulators and the X and Yindex registers. These instructions are often used to preserve program context. Forexample, pushing accumulator A onto the stack when entering a subroutine that usesaccumulator A, and then pulling accumulator A off the stack just before leaving thesubroutine, ensures that the contents of a register will be the same after returning fromthe subroutine as it was before starting the subroutine.3.1.5 Program Counter (PC)The program counter, a 16-bit register, contains the address of the next instruction tobe executed.

After reset, the program counter is initialized from one of six possiblevectors, depending on operating mode and the cause of reset.Table 3-1 Reset Vector ComparisonNormalTest or BootPOR or RESET Pin$FFFE, F$BFFE, FClock Monitor$FFFC, D$BFFC, DCOP Watchdog$FFFA, B$BFFA, B3.1.6 Condition Code Register (CCR)This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two interrupt masking bits, (IRQ and XIRQ) and a stop disable bit (S). In the M68HC11 CPU,condition codes are automatically updated by most instructions. For example, load accumulator A (LDAA) and store accumulator A (STAA) instructions automatically set orclear the N, Z, and V condition code flags.

Pushes, pulls, add B to X (ABX), add B toY (ABY), and transfer/exchange instructions do not affect the condition codes. Referto Table 3-2, which shows what condition codes are affected by a particular instruction.3.1.6.1 Carry/Borrow (C)The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during anarithmetic operation. The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate with and through the carry bit to facilitatemultiple-word shift operations.MOTOROLA3-4CENTRAL PROCESSING UNITM68HC11 E SERIESTECHNICAL DATA3.1.6.2 Overflow (V)The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the Vbit is cleared.3.1.6.3 Zero (Z)The Z bit is set if the result of an arithmetic, logic, or data manipulation operation iszero.

Otherwise, the Z bit is cleared. Compare instructions do an internal implied subtraction and the condition codes, including Z, reflect the results of that subtraction. Afew operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags.For these operations, only = and ≠ conditions can be determined.3.1.6.4 Negative (N)The N bit is set if the result of an arithmetic, logic, or data manipulation operation isnegative (MSB = 1).

Otherwise, the N bit is cleared. A result is said to be negative ifits most significant bit (MSB) is a one. A quick way to test whether the contents of amemory location has the MSB set is to load it into an accumulator and then check thestatus of the N bit.3.1.6.5 Interrupt Mask (I)The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable interrupt sources. While the I bit is set, interrupts can become pending, but the operationof the CPU continues uninterrupted until the I bit is cleared.

After any reset, the I bit isset by default and can only be cleared by a software instruction. When an interrupt isrecognized, the I bit is set after the registers are stacked, but before the interrupt vectoris fetched. After the interrupt has been serviced, a return from interrupt instruction isnormally executed, restoring the registers to the values that were present before theinterrupt occurred. Normally, the I bit is zero after a return from interrupt is executed.Although the I bit can be cleared within an interrupt service routine, "nesting" interruptsin this way should only be done when there is a clear understanding of latency and ofthe arbitration mechanism.

Refer to SECTION 5 RESETS AND INTERRUPTS.3.1.6.6 Half Carry (H)The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unitduring an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half carry isused during BCD operations.3.1.6.7 X Interrupt Mask (X)The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is setby default and must be cleared by a software instruction. When an XIRQ interrupt isrecognized, the X and I bits are set after the registers are stacked, but before the interrupt vector is fetched. After the interrupt has been serviced, an RTI instruction isnormally executed, causing the registers to be restored to the values that were presentbefore the interrupt occurred. The X interrupt mask bit is set only by hardware (RESETor XIRQ acknowledge).

X is cleared only by program instruction (TAP, where the associated bit of A is zero; or RTI, where bit 6 of the value loaded into the CCR from thestack has been cleared). There is no hardware action for clearing X.M68HC11 E SERIESTECHNICAL DATACENTRAL PROCESSING UNITMOTOROLA3-533.1.6.8 Stop Disable (S)Setting the STOP disable (S) bit prevents the STOP instruction from putting theM68HC11 into a low-power stop condition. If the STOP instruction is encountered bythe CPU while the S bit is set, it is treated as a no-operation (NOP) instruction, andprocessing continues to the next instruction. S is set by reset — STOP disabled by default.3.2 Data TypesThe M68HC11 CPU supports the following data types:3• Bit data• 8-bit and 16-bit signed and unsigned integers• 16-bit unsigned fractions• 16-bit addressesA byte is eight bits wide and can be accessed at any byte location.

A word is composedof two consecutive bytes with the most significant byte at the lower value address. Because the M68HC11 is an 8-bit CPU, there are no special requirements for alignmentof instructions or operands.3.3 Opcodes and OperandsThe M68HC11 Family of microcontrollers uses 8-bit opcodes. Each opcode identifiesa particular instruction and associated addressing mode to the CPU. Several opcodesare required to provide each instruction with a range of addressing capabilities. Only256 opcodes would be available if the range of values were restricted to the numberable to be expressed in 8-bit binary numbers.A four-page opcode map has been implemented to expand the number of instructions.An additional byte, called a prebyte, directs the processor from page 0 of the opcodemap to one of the other three pages. As its name implies, the additional byte precedesthe opcode.A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, orthree operands.

The operands contain information the CPU needs for executing theinstruction. Complete instructions can be from one to five bytes long.3.4 Addressing ModesSix addressing modes can be used to access memory: immediate, direct, extended,indexed, inherent, and relative. These modes are detailed in the following paragraphs.All modes except inherent mode use an effective address. The effective address is thememory address from which the argument is fetched or stored, or the address fromwhich execution is to proceed. The effective address can be specified within an instruction, or it can be calculated.3.4.1 ImmediateIn the immediate addressing mode an argument is contained in the byte(s) immediately following the opcode.

The number of bytes following the opcode matches the sizeMOTOROLA3-6CENTRAL PROCESSING UNITM68HC11 E SERIESTECHNICAL DATAof the register or memory location being operated on. There are two-, three-, and four(if prebyte is required) byte immediate instructions. The effective address is the address of the byte following the instruction.3.4.2 DirectIn the direct addressing mode, the low-order byte of the operand address is containedin a single byte following the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00 – $FF are thus accessed directly, using two-byte instructions. Execution time is reduced by eliminating the additional memory accessrequired for the high-order address byte. In most applications, this 256- byte area isreserved for frequently referenced data.