ATmega8 (961730), страница 45
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Secondly, the CPU itself can execute instructions incorrectly, if the supply voltagefor executing instructions is too low.Flash corruption can easily be avoided by following these design recommendations (oneis sufficient):1. If there is no need for a Boot Loader update in the system, program the BootLoader Lock Bits to prevent any Boot Loader software updates.2. Keep the AVR RESET active (low) during periods of insufficient power supplyvoltage. This can be done by enabling the internal Brown-out Detector (BOD) ifthe operating voltage matches the detection level. If not, an external low VCCReset Protection circuit can be used. If a reset occurs while a write operation isin progress, the write operation will be completed provided that the power supplyvoltage is sufficient.3.
Keep the AVR core in Power-down sleep mode during periods of low VCC. Thiswill prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCR Register and thus the Flash from unintentionalwrites.Programming Time for Flashwhen using SPMThe calibrated RC Oscillator is used to time Flash accesses. Table 81 shows the typicalprogramming time for Flash accesses from the CPU.Table 81.
SPM Programming TimeSymbolFlash write (page erase, page write,and write Lock Bits by SPM)Min Programming TimeMax Programming Time3.7 ms4.5 ms2152486O–AVR–10/04Simple Assembly CodeExample for a Boot Loader;-the routine writes one page of data from RAM to Flash; the first data location in RAM is pointed to by the Y pointer; the first data location in Flash is pointed to by the Z-pointer;-error handling is not included;-the routine must be placed inside the boot space; (at least the Do_spm sub routine). Only code inside NRWW sectioncan; be read during self-programming (page erase and page write).;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),; loophi (r25), spmcrval (r20); storing and restoring of registers is not included in the routine; register usage can be optimized at the expense of code size;-It is assumed that either the interrupt table is moved to theBoot; loader section or that the interrupts are disabled..equ PAGESIZEB = PAGESIZE*2;PAGESIZEB is page size in BYTES, notwords.org SMALLBOOTSTARTWrite_page:; page eraseldi spmcrval, (1<<PGERS) | (1<<SPMEN)rcallDo_spm; re-enable the RWW sectionldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)rcallDo_spm; transfer data from RAM to Flash page bufferldi looplo, low(PAGESIZEB);init loop variableldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256Wrloop:ldr0, Y+ldr1, Y+ldi spmcrval, (1<<SPMEN)rcallDo_spmadiw ZH:ZL, 2sbiw loophi:looplo, 2;use subi for PAGESIZEB<=256brne Wrloop; execute page writesubi ZL, low(PAGESIZEB);restore pointersbci ZH, high(PAGESIZEB);not required for PAGESIZEB<=256ldi spmcrval, (1<<PGWRT) | (1<<SPMEN)rcallDo_spm; re-enable the RWW sectionldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)rcallDo_spm; read back and check, optionalldi looplo, low(PAGESIZEB);init loop variableldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256subi YL, low(PAGESIZEB);restore pointersbci YH, high(PAGESIZEB)Rdloop:lpm r0, Z+ldr1, Y+cpse r0, r1rjmp Error216ATmega8(L)2486O–AVR–10/04ATmega8(L)sbiw loophi:looplo, 1brne Rdloop;use subi for PAGESIZEB<=256; return to RWW section; verify that RWW section is safe to readReturn:intemp1, SPMCRsbrs temp1, RWWSB; If RWWSB is set, the RWW section isnot ready yetret; re-enable the RWW sectionldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)rcallDo_spmrjmp ReturnDo_spm:; check for previous SPM completeWait_spm:intemp1, SPMCRsbrc temp1, SPMENrjmp Wait_spm; input: spmcrval determines SPM action; disable interrupts if enabled, store statusintemp2, SREGcli; check that no EEPROM write access is presentWait_ee:sbic EECR, EEWErjmp Wait_ee; SPM timed sequenceout SPMCR, spmcrvalspm; restore SREG (to enable interrupts if originally enabled)out SREG, temp2retATmega8 Boot LoaderParametersIn Table 82 through Table 84, the parameters used in the description of the self programming are given.Table 82.
Boot Size ConfigurationBootSizePagesApplicationFlashSectionBootLoaderFlashSectionEndApplicationSectionBoot ResetAddress(Start BootLoaderSection)BOOTSZ1BOOTSZ011128words40x000 0xF7F0xF80 0xFFF0xF7F0xF8010256words80x000 0xEFF0xF00 0xFFF0xEFF0xF0001512words160x000 0xDFF0xE00 0xFFF0xDFF0xE00001024words320x000 0xBFF0xC00 0xFFF0xBFF0xC002172486O–AVR–10/04Note:The different BOOTSZ Fuse configurations are shown in Figure 102.Table 83.
Read-While-Write LimitSectionPagesAddressRead-While-Write section (RWW)960x000 - 0xBFFNo Read-While-Write section (NRWW)320xC00 - 0xFFFFor details about these two section, see “NRWW – No Read-While-Write Section” onpage 207 and “RWW – Read-While-Write Section” on page 207Table 84. Explanation of Different Variables used in Figure 103 and the Mapping to theZ-pointerCorrespondingZ-value(1)VariablePCMSB11Most significant bit in the Program Counter.(The Program Counter is 12 bits PC[11:0])PAGEMSB4Most significant bit which is used to address thewords within one page (32 words in a pagerequires 5 bits PC [4:0]).ZPCMSBZ12Bit in Z-register that is mapped to PCMSB.Because Z0 is not used, the ZPCMSB equalsPCMSB + 1.ZPAGEMSBZ5Bit in Z-register that is mapped to PAGEMSB.Because Z0 is not used, the ZPAGEMSBequals PAGEMSB + 1.PCPAGEPC[11:5]Z12:Z6Program counter page address: Page select,for page erase and page writePCWORDPC[4:0]Z5:Z1Program counter word address: Word select, forfilling temporary buffer (must be zero duringpage write operation)Note:218Description1.
Z15:Z13: always ignoredZ0: should be zero for all SPM commands, byte select for the LPM instruction.See “Addressing the Flash During Self-Programming” on page 211 for details aboutthe use of Z-pointer during Self-Programming.ATmega8(L)2486O–AVR–10/04ATmega8(L)MemoryProgrammingProgram And DataMemory Lock BitsThe ATmega8 provides six Lock Bits which can be left unprogrammed (“1”) or can beprogrammed (“0”) to obtain the additional features listed in Table 86. The Lock Bits canonly be erased to “1” with the Chip Erase command.Table 85.
Lock Bit ByteDescriptionDefault Value(1)7–1 (unprogrammed)6–1 (unprogrammed)BLB125Boot lock bit1 (unprogrammed)BLB114Boot lock bit1 (unprogrammed)BLB023Boot lock bit1 (unprogrammed)BLB012Boot lock bit1 (unprogrammed)LB21Lock bit1 (unprogrammed)LB10Lock bit1 (unprogrammed)Lock Bit ByteNote:Bit No.1. “1” means unprogrammed, “0” means programmedTable 86.
Lock Bit Protection Modes(2)Memory Lock BitsProtection TypeLB ModeLB2LB1111No memory lock features enabled.0Further programming of the Flash and EEPROM isdisabled in Parallel and Serial Programming mode. TheFuse Bits are locked in both Serial and ParallelProgramming mode.(1)Further programming and verification of the Flash andEEPROM is disabled in parallel and Serial Programmingmode.
The Fuse Bits are locked in both Serial and ParallelProgramming modes.(1)21300BLB0 ModeBLB02BLB01111No restrictions for SPM or LPM accessing the Applicationsection.210SPM is not allowed to write to the Application section.0SPM is not allowed to write to the Application section, andLPM executing from the Boot Loader section is notallowed to read from the Application section. If InterruptVectors are placed in the Boot Loader section, interruptsare disabled while executing from the Application section.LPM executing from the Boot Loader section is notallowed to read from the Application section. If InterruptVectors are placed in the Boot Loader section, interruptsare disabled while executing from the Application section.30401BLB1 ModeBLB12BLB112192486O–AVR–10/04Table 86.
Lock Bit Protection Modes(2) (Continued)Memory Lock Bits111No restrictions for SPM or LPM accessing the Boot Loadersection.210SPM is not allowed to write to the Boot Loader section.0SPM is not allowed to write to the Boot Loader section,and LPM executing from the Application section is notallowed to read from the Boot Loader section. If InterruptVectors are placed in the Application section, interruptsare disabled while executing from the Boot Loader section.1LPM executing from the Application section is not allowedto read from the Boot Loader section. If Interrupt Vectorsare placed in the Application section, interrupts aredisabled while executing from the Boot Loader section.304Notes:Fuse BitsProtection Type01. Program the Fuse Bits before programming the Lock Bits.2.
“1” means unprogrammed, “0” means programmedThe ATmega8 has two fuse bytes. Table 87 and Table 88 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses areread as logical zero, “0”, if they are programmed.Table 87. Fuse High ByteFuse HighByteBitNo.RSTDISBL(4)7WDTON6SPIEN(1)DescriptionDefault ValueSelect if PC6 is I/O pin or RESET pin1 (unprogrammed, PC6 isRESET-pin)WDT always on1 (unprogrammed, WDTenabled by WDTCR)5Enable Serial Program and DataDownloading0 (programmed, SPI prog.enabled)CKOPT(2)4Oscillator options1 (unprogrammed)EESAVE3EEPROM memory is preservedthrough the Chip Erase1 (unprogrammed,EEPROM not preserved)BOOTSZ12Select Boot Size (see Table 82 fordetails)0 (programmed)(3)BOOTSZ01Select Boot Size (see Table 82 fordetails)0 (programmed)(3)BOOTRST0Select Reset Vector1 (unprogrammed)Notes:2201.
The SPIEN Fuse is not accessible in Serial Programming mode.2. The CKOPT Fuse functionality depends on the setting of the CKSEL bits, see “ClockSources” on page 24 for details.3. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 82 onpage 217.4. When programming the RSTDISBL Fuse Parallel Programming has to be used tochange fuses or perform further programming.ATmega8(L)2486O–AVR–10/04ATmega8(L)Table 88. Fuse Low ByteFuse LowByteBitNo.BODLEVELDescriptionDefault Value7Brown out detector trigger level1 (unprogrammed)BODEN6Brown out detector enable1 (unprogrammed, BOD disabled)SUT15Select start-up time1 (unprogrammed)(1)SUT04Select start-up time0 (programmed)(1)CKSEL33Select Clock source0 (programmed)(2)CKSEL22Select Clock source0 (programmed)(2)CKSEL11Select Clock source0 (programmed)(2)CKSEL00Select Clock source1 (unprogrammed)(2)Notes:1.
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