ATmega8 (961730), страница 40
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To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set.• Bits 1,0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode SelectThese bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 71.Table 71. ACIS1/ACIS0 SettingsACIS1ACIS0Interrupt Mode00Comparator Interrupt on Output Toggle01Reserved10Comparator Interrupt on Falling Output Edge11Comparator Interrupt on Rising Output Edge1912486O–AVR–10/04When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register.
Otherwise an interruptcan occur when the bits are changed.Analog ComparatorMultiplexed InputIt is possible to select any of the ADC7..0(1) pins to replace the negative input to theAnalog Comparator. The ADC multiplexer is used to select this input, and consequentlythe ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in SFIOR) is set and the ADC is switched off (ADEN inADCSRA is zero), MUX2..0 in ADMUX select the input pin to replace the negative inputto the Analog Comparator, as shown in Table 72.
If ACME is cleared or ADEN is set,AIN1 is applied to the negative input to the Analog Comparator.Table 72. Analog Comparator Multiplexed Input(1)ACMEADENMUX2..00xxxxAIN111xxxAIN110000ADC010001ADC110010ADC210011ADC310100ADC410101ADC510110ADC610111ADC7Note:192Analog Comparator Negative Input1. ADC7..6 are only available in TQFP and MLF Package.ATmega8(L)2486O–AVR–10/04ATmega8(L)Analog-to-DigitalConverterFeatures•••••••••••••10-bit Resolution0.5 LSB Integral Non-linearity± 2 LSB Absolute Accuracy13 - 260 µs Conversion TimeUp to 15 kSPS at Maximum Resolution6 Multiplexed Single Ended Input Channels2 Additional Multiplexed Single Ended Input Channels (TQFP and MLF Package only)Optional Left Adjustment for ADC Result Readout0 - VCC ADC Input Voltage RangeSelectable 2.56V ADC Reference VoltageFree Running or Single Conversion ModeInterrupt on ADC Conversion CompleteSleep Mode Noise CancelerThe ATmega8 features a 10-bit successive approximation ADC.
The ADC is connectedto an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port C. The single-ended voltage inputs refer to 0V (GND).The ADC contains a Sample and Hold circuit which ensures that the input voltage to theADC is held at a constant level during conversion.
A block diagram of the ADC is shownin Figure 90.The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ morethan ± 0.3V from VCC. See the paragraph “ADC Noise Canceler” on page 198 on how toconnect this pin.Internal reference voltages of nominally 2.56V or AVCC are provided On-chip.
The voltage reference may be externally decoupled at the AREF pin by a capacitor for betternoise performance.1932486O–AVR–10/04Figure 90. Analog to Digital Converter Block Schematic OperationADC CONVERSIONCOMPLETE IRQ15ADC[9:0]ADPS1ADPS0ADPS2ADIFADFRADENADSC0ADC DATA REGISTER(ADCH/ADCL)ADC CTRL. & STATUSREGISTER (ADCSRA)MUX0MUX2MUX1MUX3ADLARREFS0REFS1ADC MULTIPLEXERSELECT (ADMUX)ADIEADIF8-BIT DATA BUSMUX DECODERCHANNEL SELECTIONPRESCALERAVCCCONVERSION LOGICINTERNAL 2.56VREFERENCESAMPLE & HOLDCOMPARATORAREF10-BIT DAC+GNDBANDGAPREFERENCEADC7ADC6ADC5INPUTMUXADC MULTIPLEXEROUTPUTADC4ADC3ADC2ADC1ADC0The ADC converts an analog input voltage to a 10-bit digital value through successiveapproximation.
The minimum value represents GND and the maximum value representsthe voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in theADMUX Register. The internal voltage reference may thus be decoupled by an externalcapacitor at the AREF pin to improve noise immunity.The analog input channel is selected by writing to the MUX bits in ADMUX. Any of theADC input pins, as well as GND and a fixed bandgap voltage reference, can be selectedas single ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit,ADEN in ADCSRA.
Voltage reference and input channel selections will not go into effectuntil ADEN is set. The ADC does not consume power when ADEN is cleared, so it isrecommended to switch off the ADC before entering power saving sleep modes.The ADC generates a 10-bit result which is presented in the ADC Data Registers,ADCH and ADCL. By default, the result is presented right adjusted, but can optionallybe presented left adjusted by setting the ADLAR bit in ADMUX.194ATmega8(L)2486O–AVR–10/04ATmega8(L)If the result is left adjusted and no more than 8-bit precision is required, it is sufficient toread ADCH.
Otherwise, ADCL must be read first, then ADCH, to ensure that the contentof the Data Registers belongs to the same conversion. Once ADCL is read, ADC accessto Data Registers is blocked. This means that if ADCL has been read, and a conversioncompletes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers isre-enabled.The ADC has its own interrupt which can be triggered when a conversion completes.When ADC access to the Data Registers is prohibited between reading of ADCH andADCL, the interrupt will trigger even if the result is lost.Starting a ConversionA single conversion is started by writing a logical one to the ADC Start Conversion bit,ADSC.
This bit stays high as long as the conversion is in progress and will be cleared byhardware when the conversion is completed. If a different data channel is selected whilea conversion is in progress, the ADC will finish the current conversion before performingthe channel change.In Free Running mode, the ADC is constantly sampling and updating the ADC DataRegister. Free Running mode is selected by writing the ADFR bit in ADCSRA to one.The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
In this mode the ADC will perform successive conversions independently ofwhether the ADC Interrupt Flag, ADIF is cleared or not.Prescaling andConversion TimingFigure 91. ADC PrescalerADENSTARTReset7-BIT ADC PRESCALERCK/128CK/64CK/32CK/16CK/8CK/4CK/2CKADPS0ADPS1ADPS2ADC CLOCK SOURCEBy default, the successive approximation circuitry requires an input clock frequencybetween 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get ahigher sample rate.The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz.
The prescaling is set by the ADPS bitsin ADCSRA. The prescaler starts counting from the moment the ADC is switched on bysetting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADENbit is set, and is continuously reset when ADEN is low.When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion1952486O–AVR–10/04takes 13 ADC clock cycles.
The first conversion after the ADC is switched on (ADEN inADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normalconversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. Insingle conversion mode, ADSC is cleared simultaneously. The software may then setADSC again, and a new conversion will be initiated on the first rising ADC clock edge.In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high.
For a summary of conversion times, seeTable 73.Figure 92. ADC Timing Diagram, First Conversion (Single Conversion Mode)NextConversionFirst ConversionCycle Number121213141516171819202122232425123ADC ClockADENADSCADIFADCHMSB of ResultADCLLSB of ResultMUX and REFSUpdateConversionCompleteSample & HoldMUX and REFSUpdateFigure 93. ADC Timing Diagram, Single ConversionOne ConversionCycle Number123456789Next Conversion10111213123ADC ClockADSCADIFADCHMSB of ResultADCLLSB of ResultSample & HoldMUX and REFSUpdate196ConversionCompleteMUX and REFSUpdateATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 94.
ADC Timing Diagram, Free Running ConversionOne ConversionCycle Number1112Next Conversion131234ADC ClockADSCADIFADCHMSB of ResultADCLLSB of ResultSample &HoldConversionCompleteMUX and REFSUpdateTable 73. ADC Conversion TimeSample & Hold (Cyclesfrom Start of Conversion)Conversion Time(Cycles)Extended conversion13.525Normal conversions, single ended1.513ConditionChanging Channel orReference SelectionThe MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access.
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