ATmega8 (961730), страница 35
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As long as the TWINT Flag isset, the SCL line is held low. This allows the application software to complete its tasksbefore allowing the TWI transmission to continue.The TWINT Flag is set in the following situations:•After the TWI has transmitted a START/REPEATED START condition.•After the TWI has transmitted SLA+R/W.•After the TWI has transmitted an address byte.•After the TWI has lost arbitration.•After the TWI has been addressed by own slave address or general call.•After the TWI has received a data byte.•After a STOP or REPEATED START has been received while still addressed as aSlave.•When a bus error has occurred due to an illegal START or STOP condition.TWI Register DescriptionTWI Bit Rate Register – TWBRBit76543210TWBR7TWBR6TWBR5TWBR4TWBR3TWBR2TWBR1TWBR0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000TWBR• Bits 7..0 – TWI Bit Rate RegisterTWBR selects the division factor for the bit rate generator.
The bit rate generator is afrequency divider which generates the SCL clock frequency in the Master modes. See“Bit Rate Generator Unit” on page 167 for calculating bit rates.TWI Control Register – TWCRBit76543210TWINTTWEATWSTATWSTOTWWCTWEN–TWIERead/WriteR/WR/WR/WR/WRR/WRR/WInitial Value00000000TWCRThe TWCR is used to control the operation of the TWI. It is used to enable the TWI, toinitiate a Master access by applying a START condition to the bus, to generate aReceiver acknowledge, to generate a stop condition, and to control halting of the buswhile the data to be written to the bus are written to the TWDR. It also indicates a writecollision if data is attempted written to TWDR while the register is inaccessible.• Bit 7 – TWINT: TWI Interrupt FlagThis bit is set by hardware when the TWI has finished its current job and expects application software response.
If the I-bit in SREG and TWIE in TWCR are set, the MCU willjump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period isstretched. The TWINT Flag must be cleared by software by writing a logic one to it. Notethat this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses tothe TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag.• Bit 6 – TWEA: TWI Enable Acknowledge Bit168ATmega8(L)2486O–AVR–10/04ATmega8(L)The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions aremet:1.
The device’s own slave address has been received.2. A general call has been received, while the TWGCE bit in the TWAR is set.3. A data byte has been received in Master Receiver or Slave Receiver mode.By writing the TWEA bit to zero, the device can be virtually disconnected from the Twowire Serial Bus temporarily. Address recognition can then be resumed by writing theTWEA bit to one again.• Bit 5 – TWSTA: TWI START Condition BitThe application writes the TWSTA bit to one when it desires to become a Master on theTwo-wire Serial Bus. The TWI hardware checks if the bus is available, and generates aSTART condition on the bus if it is free.
However, if the bus is not free, the TWI waitsuntil a STOP condition is detected, and then generates a new START condition to claimthe bus Master status. TWSTA must be cleared by software when the START conditionhas been transmitted.• Bit 4 – TWSTO: TWI STOP Condition BitWriting the TWSTO bit to one in Master mode will generate a STOP condition on theTwo-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bitis cleared automatically.
In Slave mode, setting the TWSTO bit can be used to recoverfrom an error condition. This will not generate a STOP condition, but the TWI returns toa well-defined unaddressed Slave mode and releases the SCL and SDA lines to a highimpedance state.• Bit 3 – TWWC: TWI Write Collision FlagThe TWWC bit is set when attempting to write to the TWI Data Register – TWDR whenTWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.• Bit 2 – TWEN: TWI Enable BitThe TWEN bit enables TWI operation and activates the TWI interface.
When TWEN iswritten to one, the TWI takes control over the I/O pins connected to the SCL and SDApins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWIis switched off and all TWI transmissions are terminated, regardless of any ongoingoperation.• Bit 1 – Res: Reserved BitThis bit is a reserved bit and will always read as zero.• Bit 0 – TWIE: TWI Interrupt EnableWhen this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request willbe activated for as long as the TWINT Flag is high.1692486O–AVR–10/04TWI Status Register – TWSRBit76543210TWS7TWS6TWS5TWS4TWS3–TWPS1TWPS0Read/WriteRRRRRRR/WR/WInitial Value11111000TWSR• Bits 7..3 – TWS: TWI StatusThese 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status codes are described later in this section.
Note that the value read from TWSRcontains both the 5-bit status value and the 2-bit prescaler value. The applicationdesigner should mask the prescaler bits to zero when checking the Status bits. Thismakes status checking independent of prescaler setting.
This approach is used in thisdatasheet, unless otherwise noted.• Bit 2 – Res: Reserved BitThis bit is reserved and will always read as zero.• Bits 1..0 – TWPS: TWI Prescaler BitsThese bits can be read and written, and control the bit rate prescaler.Table 65. TWI Bit Rate PrescalerTWPS1TWPS0Prescaler Value00101410161164To calculate bit rates, see “Bit Rate Generator Unit” on page 167.
The value ofTWPS1..0 is used in the equation.TWI Data Register – TWDRBit76543210TWD7TWD6TWD5TWD4TWD3TWD2TWD1TWD0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value11111111TWDRIn Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, theTWDR contains the last byte received. It is writable while the TWI is not in the process ofshifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware.Note that the Data Register cannot be initialized by the user before the first interruptoccurs. The data in TWDR remains stable as long as TWINT is set. While data is shiftedout, data on the bus is simultaneously shifted in. TWDR always contains the last bytepresent on the bus, except after a wake up from a sleep mode by the TWI interrupt. Inthis case, the contents of TWDR is undefined.
In the case of a lost bus arbitration, nodata is lost in the transition from Master to Slave. Handling of the ACK bit is controlledautomatically by the TWI logic, the CPU cannot access the ACK bit directly.• Bits 7..0 – TWD: TWI Data RegisterThese eight bits constitute the next data byte to be transmitted, or the latest data bytereceived on the Two-wire Serial Bus.TWI (Slave) Address Register– TWAR170Bit76543210ATmega8(L)2486O–AVR–10/04ATmega8(L)TWA6TWA5TWA4TWA3TWA2TWA1TWA0TWGCERead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value11111110TWARThe TWAR should be loaded with the 7-bit Slave address (in the seven most significantbits of TWAR) to which the TWI will respond when programmed as a Slave Transmitteror Receiver, and not needed in the Master modes.
In multimaster systems, TWAR mustbe set in masters which can be addressed as Slaves by other Masters.The LSB of TWAR is used to enable recognition of the general call address (0x00).There is an associated address comparator that looks for the slave address (or generalcall address if enabled) in the received serial address.
If a match is found, an interruptrequest is generated.• Bits 7..1 – TWA: TWI (Slave) Address RegisterThese seven bits constitute the slave address of the TWI unit.• Bit 0 – TWGCE: TWI General Call Recognition Enable BitIf set, this bit enables the recognition of a General Call given over the Two-wire SerialBus.Using the TWIThe AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all busevents, like reception of a byte or transmission of a START condition. Because the TWIis interrupt-based, the application software is free to carry on other operations during aTWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together withthe Global Interrupt Enable bit in SREG allow the application to decide whether or notassertion of the TWINT Flag should generate an interrupt request. If the TWIE bit iscleared, the application must poll the TWINT Flag in order to detect actions on the TWIbus.When the TWINT Flag is asserted, the TWI has finished an operation and awaits application response.
In this case, the TWI Status Register (TWSR) contains a valueindicating the current state of the TWI bus. The application software can then decidehow the TWI should behave in the next TWI bus cycle by manipulating the TWCR andTWDR Registers.Figure 77 is a simple example of how the application can interface to the TWI hardware.In this example, a Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed explanation follows later in this section. A simplecode example implementing the desired behavior is also presented.1712486O–AVR–10/04ApplicationActionFigure 77. Interfacing the Application to the TWI in a Typical Transmission1. Applicationwrites to TWCR toinitiatetransmission ofSTARTTWIHardwareActionTWI bus3.
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