ATmega8 (961730), страница 32
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The FE bit is zero when the stop bit ofreceived data is one. Always set this bit to zero when writing to UCSRA.• Bit 3 – DOR: Data OverRunThis bit is set if a Data OverRun condition is detected. A Data OverRun occurs when thereceive buffer is full (two characters), it is a new character waiting in the Receive ShiftRegister, and a new start bit is detected. This bit is valid until the receive buffer (UDR) isread. Always set this bit to zero when writing to UCSRA.• Bit 2 – PE: Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when receivedand the parity checking was enabled at that point (UPM1 = 1). This bit is valid until thereceive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.• Bit 1 – U2X: Double the USART transmission speed1512486O–AVR–10/04This bit only has effect for the asynchronous operation.
Write this bit to zero when usingsynchronous operation.Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.• Bit 0 – MPCM: Multi-processor Communication ModeThis bit enables the Multi-processor Communication mode. When the MPCM bit is written to one, all the incoming frames received by the USART Receiver that do not containaddress information will be ignored. The Transmitter is unaffected by the MPCM setting.For more detailed information see “Multi-processor Communication Mode” on page 148.USART Control and StatusRegister B – UCSRBBit76543210RXCIETXCIEUDRIERXENTXENUCSZ2RXB8TXB8Read/WriteR/WR/WR/WR/WR/WR/WRR/WInitial Value00000000UCSRB• Bit 7 – RXCIE: RX Complete Interrupt EnableWriting this bit to one enables interrupt on the RXC Flag.
A USART Receive Completeinterrupt will be generated only if the RXCIE bit is written to one, the Global InterruptFlag in SREG is written to one and the RXC bit in UCSRA is set.• Bit 6 – TXCIE: TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC Flag. A USART Transmit Completeinterrupt will be generated only if the TXCIE bit is written to one, the Global InterruptFlag in SREG is written to one and the TXC bit in UCSRA is set.• Bit 5 – UDRIE: USART Data Register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDRE Flag. A Data Register Empty interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag inSREG is written to one and the UDRE bit in UCSRA is set.• Bit 4 – RXEN: Receiver EnableWriting this bit to one enables the USART Receiver.
The Receiver will override normalport operation for the RxD pin when enabled. Disabling the Receiver will flush thereceive buffer invalidating the FE, DOR and PE Flags.• Bit 3 – TXEN: Transmitter EnableWriting this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin when enabled. The disabling of the Transmitter(writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed (i.e., when the Transmit Shift Register and Transmit Buffer Registerdo not contain data to be transmitted). When disabled, the Transmitter will no longeroverride the TxD port.• Bit 2 – UCSZ2: Character SizeThe UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits(Character Size) in a frame the Receiver and Transmitter use.• Bit 1 – RXB8: Receive Data Bit 8RXB8 is the ninth data bit of the received character when operating with serial frameswith nine data bits.
Must be read before reading the low bits from UDR.• Bit 0 – TXB8: Transmit Data Bit 8152ATmega8(L)2486O–AVR–10/04ATmega8(L)TXB8 is the ninth data bit in the character to be transmitted when operating with serialframes with nine data bits. Must be written before writing the low bits to UDR.USART Control and StatusRegister C – UCSRCBit76543210URSELUMSELUPM1UPM0USBSUCSZ1UCSZ0UCPOLRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value10000110UCSRCThe UCSRC Register shares the same I/O location as the UBRRH Register. See the“Accessing UBRRH/UCSRC Registers” on page 149 section which describes how toaccess this register.• Bit 7 – URSEL: Register SelectThis bit selects between accessing the UCSRC or the UBRRH Register. It is read asone when reading UCSRC.
The URSEL must be one when writing the UCSRC.• Bit 6 – UMSEL: USART Mode SelectThis bit selects between Asynchronous and Synchronous mode of operation.Table 55. UMSEL Bit SettingsUMSELMode0Asynchronous Operation1Synchronous Operation1532486O–AVR–10/04• Bit 5:4 – UPM1:0: Parity ModeThese bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits withineach frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.
If a mismatch is detected, the PE Flag in UCSRA will be set.Table 56. UPM Bits SettingsUPM1UPM0Parity Mode00Disabled01Reserved10Enabled, Even Parity11Enabled, Odd Parity• Bit 3 – USBS: Stop Bit SelectThis bit selects the number of stop bits to be inserted by the trAnsmitter. The Receiverignores this setting.Table 57. USBS Bit SettingsUSBSStop Bit(s)01-bit12-bit• Bit 2:1 – UCSZ1:0: Character SizeThe UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits(Character Size) in a frame the Receiver and Transmitter use.Table 58. UCSZ Bits SettingsUCSZ2UCSZ1UCSZ0Character Size0005-bit0016-bit0107-bit0118-bit100Reserved101Reserved110Reserved1119-bit• Bit 0 – UCPOL: Clock Polarity154ATmega8(L)2486O–AVR–10/04ATmega8(L)This bit is used for Synchronous mode only. Write this bit to zero when Asynchronousmode is used.
The UCPOL bit sets the relationship between data output change anddata input sample, and the synchronous clock (XCK).Table 59. UCPOL Bit SettingsTransmitted Data Changed (Output ofTxD Pin)Received Data Sampled (Input onRxD Pin)0Rising XCK EdgeFalling XCK Edge1Falling XCK EdgeRising XCK EdgeUCPOLUSART Baud Rate Registers –UBRRL and UBRRHsBit15141312URSEL–––111098UBRR[11:8]UBRRHUBRR[7:0]7Read/WriteInitial Value65UBRRL43210R/WRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W0000000000000000The UBRRH Register shares the same I/O location as the UCSRC Register. See the“Accessing UBRRH/UCSRC Registers” on page 149 section which describes how toaccess this register.• Bit 15 – URSEL: Register SelectThis bit selects between accessing the UBRRH or the UCSRC Register. It is read aszero when reading UBRRH. The URSEL must be zero when writing the UBRRH.• Bit 14:12 – Reserved BitsThese bits are reserved for future use.
For compatibility with future devices, these bitmust be written to zero when UBRRH is written.• Bit 11:0 – UBRR11:0: USART Baud Rate RegisterThis is a 12-bit register which contains the USART baud rate. The UBRRH contains thefour most significant bits, and the UBRRL contains the eight least significant bits of theUSART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update ofthe baud rate prescaler.1552486O–AVR–10/04Examples of Baud RateSettingFor standard crystal and resonator frequencies, the most commonly used baud rates forasynchronous operation can be generated by using the UBRR settings in Table 60.UBRR values which yield an actual baud rate differing less than 0.5% from the targetbaud rate, are bold in the table.
Higher error ratings are acceptable, but the Receiver willhave less noise resistance when the error ratings are high, especially for large serialframes (see “Asynchronous Operational Range” on page 146). The error values are calculated using the following equation:BaudRate Closest Match- – 1⎞⎠ • 100%Error[%] = ⎛⎝ ------------------------------------------------------BaudRateTable 60. Examples of UBRR Settings for Commonly Used Oscillator Frequenciesfosc = 1.0000 MHzfosc = 1.8432 MHzfosc = 2.0000 MHzBaudRate(bps)UBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRError2400250.2%510.2%470.0%950.0%510.2%1030.2%4800120.2%250.2%230.0%470.0%250.2%510.2%96006-7.0%120.2%110.0%230.0%120.2%250.2%14.4k38.5%8-3.5%70.0%150.0%8-3.5%162.1%19.2k28.5%6-7.0%50.0%110.0%6-7.0%120.2%28.8k18.5%38.5%30.0%70.0%38.5%8-3.5%38.4k1-18.6%28.5%20.0%50.0%28.5%6-7.0%57.6k08.5%18.5%10.0%30.0%18.5%38.5%76.8k––1-18.6%1-25.0%20.0%1-18.6%28.5%115.2k––08.5%00.0%10.0%08.5%18.5%230.4k––––––00.0%–-––250k––––––––––00.0%Max1.156(1)U2X = 0U2X = 162.5 kbps125 kbpsU2X = 0U2X = 1115.2 kbpsU2X = 0230.4 kbps125 kbpsU2X = 1250 kbpsUBRR = 0, Error = 0.0%ATmega8(L)2486O–AVR–10/04ATmega8(L)Table 61.
Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)fosc = 3.6864 MHzfosc = 4.0000 MHzfosc = 7.3728 MHzBaudRate(bps)UBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRError2400950.0%1910.0%1030.2%2070.2%1910.0%3830.0%4800470.0%950.0%510.2%1030.2%950.0%1910.0%9600230.0%470.0%250.2%510.2%470.0%950.0%14.4k150.0%310.0%162.1%34-0.8%310.0%630.0%19.2k110.0%230.0%120.2%250.2%230.0%470.0%28.8k70.0%150.0%8-3.5%162.1%150.0%310.0%38.4k50.0%110.0%6-7.0%120.2%110.0%230.0%57.6k30.0%70.0%38.5%8-3.5%70.0%150.0%76.8k20.0%50.0%28.5%6-7.0%50.0%110.0%115.2k10.0%30.0%18.5%38.5%30.0%70.0%230.4k00.0%10.0%08.5%18.5%10.0%30.0%250k0-7.8%1-7.8%00.0%10.0%1-7.8%3-7.8%0.5M––0-7.8%––00.0%0-7.8%1-7.8%1M––––––––––0-7.8%Max1.U2X = 0(1)U2X = 1230.4 kbpsU2X = 0460.8 kbps250 kbpsU2X = 1U2X = 00.5 MbpsU2X = 1460.8 kbps921.6 kbpsUBRR = 0, Error = 0.0%1572486O–AVR–10/04Table 62.
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