ATmega8 (961730), страница 34
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Special concerns haveSystems, Arbitration and been taken in order to ensure that transmissions will proceed as normal, even if two ormore masters initiate a transmission at the same time. Two problems arise in multi-masSynchronizationter systems:•An algorithm must be implemented allowing only one of the masters to complete thetransmission. All other masters should cease transmission when they discover thatthey have lost the selection process. This selection process is called arbitration.When a contending master discovers that it has lost the arbitration process, itshould immediately switch to Slave mode to check whether it is being addressed bythe winning master. The fact that multiple masters have started transmission at thesame time should not be detectable to the slaves, i.e. the data being transferred onthe bus must not be corrupted.•Different masters may use different SCL frequencies.
A scheme must be devised tosynchronize the serial clocks from all masters, in order to let the transmissionproceed in a lockstep fashion. This will facilitate the arbitration process.The wired-ANDing of the bus lines is used to solve both these problems. The serialclocks from all masters will be wired-ANDed, yielding a combined clock with a highperiod equal to the one from the Master with the shortest high period. The low period ofthe combined clock is equal to the low period of the Master with the longest low period.Note that all masters listen to the SCL line, effectively starting to count their SCL highand low time-out periods when the combined SCL line goes high or low, respectively.Figure 74. SCL Synchronization Between Multiple MastersTA lowTA highSCL fromMaster ASCL fromMaster BSCL BusLineTBlowMasters StartCounting Low PeriodTBhighMasters StartCounting High PeriodArbitration is carried out by all masters continuously monitoring the SDA line after outputting data.
If the value read from the SDA line does not match the value the Masterhad output, it has lost the arbitration. Note that a Master can only lose arbitration when itoutputs a high SDA value while another Master outputs a low value. The losing Mastershould immediately go to Slave mode, checking if it is being addressed by the winningMaster. The SDA line should be left high, but losing masters are allowed to generate aclock signal until the end of the current data or address packet. Arbitration will continueuntil only one Master remains, and this may take many bits.
If several masters are tryingto address the same Slave, arbitration will continue into the data packet.164ATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 75. Arbitration Between Two MastersSTARTSDA fromMaster AMaster A LosesArbitration, SDAA SDASDA fromMaster BSDA LineSynchronizedSCL LineNote that arbitration is not allowed between:•A REPEATED START condition and a data bit.•A STOP condition and a data bit.•A REPEATED START and a STOP condition.It is the user software’s responsibility to ensure that these illegal arbitration conditionsnever occur. This implies that in multi-master systems, all data transfers must use thesame composition of SLA+R/W and data packets.
In other words: All transmissionsmust contain the same number of data packets, otherwise the result of the arbitration isundefined.1652486O–AVR–10/04Overview of the TWIModuleThe TWI module is comprised of several submodules, as shown in Figure 76. All registers drawn in a thick line are accessible through the AVR data bus.Figure 76. Overview of the TWI ModuleSlew-rateControlSDASpikeFilterSlew-rateControlSpikeFilterBus Interface UnitSTART / STOPControlSpike SuppressionArbitration detectionAddress/Data ShiftRegister (TWDR)Address Match UnitAddress Register(TWAR)Address ComparatorSCL and SDA Pins166Bit Rate GeneratorPrescalerBit Rate Register(TWBR)AckControl UnitStatus Register(TWSR)Control Register(TWCR)State Machine andStatus controlTWI UnitSCLThese pins interface the AVR TWI with the rest of the MCU system.
The output driverscontain a slew-rate limiter in order to conform to the TWI specification. The input stagescontain a spike suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding tothe SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can insome systems eliminate the need for external ones.ATmega8(L)2486O–AVR–10/04ATmega8(L)Bit Rate Generator UnitThis unit controls the period of SCL when operating in a Master mode. The SCL periodis controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits inthe TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higherthan the SCL frequency.
Note that slaves may prolong the SCL low period, therebyreducing the average TWI bus clock period. The SCL frequency is generated accordingto the following equation:CPU Clock frequencySCL frequency = ---------------------------------------------------------TWPS16 + 2(TWBR) ⋅ 4•TWBR = Value of the TWI Bit Rate Register.•TWPS = Value of the prescaler bits in the TWI Status Register.Note:Bus Interface UnitTWBR should be 10 or higher if the TWI operates in Master mode.
If TWBR is lower than10, the Master may produce an incorrect output on SDA and SCL for the reminder of thebyte. The problem occurs when operating the TWI in Master mode, sending Start + SLA+ R/W to a Slave (a Slave does not need to be connected to the bus for the condition tohappen).This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware.
The TWDR contains the address or databytes to be transmitted, or the address or data bytes received. In addition to the 8-bitTWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to betransmitted or received. This (N)ACK Register is not directly accessible by the application software. However, when receiving, it can be set or cleared by manipulating theTWI Control Register (TWCR). When in Transmitter mode, the value of the received(N)ACK bit can be determined by the value in the TWSR.The START/STOP Controller is responsible for generation and detection of START,REPEATED START, and STOP conditions.
The START/STOP controller is able todetect START and STOP conditions even when the AVR MCU is in one of the sleepmodes, enabling the MCU to wake up if addressed by a Master.If the TWI has initiated a transmission as Master, the Arbitration Detection hardwarecontinuously monitors the transmission trying to determine if arbitration is in process. Ifthe TWI has lost an arbitration, the Control Unit is informed. Correct action can then betaken and appropriate status codes generated.Address Match UnitThe Address Match unit checks if received address bytes match the seven-bit addressin the TWI Address Register (TWAR). If the TWI General Call Recognition Enable(TWGCE) bit in the TWAR is written to one, all incoming address bits will also be compared against the General Call address.
Upon an address match, the Control Unit isinformed, allowing correct action to be taken. The TWI may or may not acknowledge itsaddress, depending on settings in the TWCR. The Address Match unit is able to compare addresses even when the AVR MCU is in sleep mode, enabling the MCU to wakeup if addressed by a Master.
If another interrupt (e.g., INT0) occurs during TWI Powerdown address match and wakes up the CPU, the TWI aborts operation and return to it’sidle state. If this cause any problems, ensure that TWI Address Match is the onlyenabled interrupt when entering Power-down.Control UnitThe Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR).
When an event requiring the attention of theapplication occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In thenext clock cycle, the TWI Status Register (TWSR) is updated with a status code identifying the event. The TWSR only contains relevant status information when the TWI1672486O–AVR–10/04Interrupt Flag is asserted. At all other times, the TWSR contains a special status codeindicating that no relevant status information is available.
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