ATmega8 (961730), страница 47
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Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset.Figure 105. Addressing the Flash which is Organized in Pages(1)PCMSBPROGRAMCOUNTERPAGEMSBPCPAGEPAGE ADDRESSWITHIN THE FLASHPROGRAM MEMORYPAGEPCWORDWORD ADDRESSWITHIN A PAGEPAGEINSTRUCTION WORDPCWORD[PAGEMSB:0]:000102PAGEENDNote:1. PCPAGE and PCWORD are listed in Table 89 on page 222.2272486O–AVR–10/04Figure 106. Programming the Flash Waveforms(1)FADATA0x10BADDR. LOWCDATA LOWDEBCDEDATA HIGHXXADDR. LOWDATA LOWDATA HIGHXXGADDR. HIGHHXXXA1XA0BS1XTAL1WRRDY/BSYRESET +12VOEPAGELBS2Note:Programming the EEPROM1.
“XX” is don’t care. The letters refer to the programming description above.The EEPROM is organized in pages, see Table 90 on page 222. When programmingthe EEPROM, the program data is latched into a page buffer. This allows one page ofdata to be programmed simultaneously. The programming algorithm for the EEPROMData memory is as follows (refer to “Programming the Flash” on page 226 for details onCommand, Address and Data loading):1. A: Load Command “0001 0001”.2.
G: Load Address High byte (0x00 - 0xFF).3. B: Load Address Low byte (0x00 - 0xFF).4. C: Load Data (0x00 - 0xFF).5. E: Latch data (give PAGEL a positive pulse).K: Repeat 3 through 5 until the entire buffer is filled.L: Program EEPROM page.1. Set BS1 to “0”.2. Give WR a negative pulse. This starts programming of the EEPROM page.RDY/BSY goes low.3. Wait until to RDY/BSY goes high before programming the next page.(See Figure 107 for signal waveforms).228ATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 107.
Programming the EEPROM WaveformsKADATA0x11GADDR. HIGHBCADDR. LOWDATAEXXBADDR. LOWCDATAELXXXA1XA0BS1XTAL1WRRDY/BSYRESET +12VOEPAGELBS2Reading the FlashThe algorithm for reading the Flash memory is as follows (refer to “Programming theFlash” on page 226 for details on Command and Address loading):1. A: Load Command “0000 0010”.2.
G: Load Address High byte (0x00 - 0xFF).3. B: Load Address Low byte (0x00 - 0xFF).4. Set OE to “0”, and BS1 to “0”. The Flash word Low byte can now be read atDATA.5. Set BS1 to “1”. The Flash word High byte can now be read at DATA.6. Set OE to “1”.Reading the EEPROMThe algorithm for reading the EEPROM memory is as follows (refer to “Programming theFlash” on page 226 for details on Command and Address loading):1. A: Load Command “0000 0011”.2. G: Load Address High byte (0x00 - 0xFF).3.
B: Load Address Low byte (0x00 - 0xFF).4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read atDATA.5. Set OE to “1”.Programming the Fuse LowBitsThe algorithm for programming the Fuse Low bits is as follows (refer to “Programmingthe Flash” on page 226 for details on Command and Data loading):1. A: Load Command “0100 0000”.2. C: Load Data Low byte.
Bit n = “0” programs and bit n = “1” erases the Fuse bit.3. Set BS1 and BS2 to “0”.4. Give WR a negative pulse and wait for RDY/BSY to go high.2292486O–AVR–10/04Programming the Fuse HighBitsThe algorithm for programming the Fuse high bits is as follows (refer to “Programmingthe Flash” on page 226 for details on Command and Data loading):1. A: Load Command “0100 0000”.2. C: Load Data Low byte.
Bit n = “0” programs and bit n = “1” erases the Fuse bit.3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.4. Give WR a negative pulse and wait for RDY/BSY to go high.5. Set BS1 to “0”. This selects low data byte.Programming the Lock BitsThe algorithm for programming the Lock Bits is as follows (refer to “Programming theFlash” on page 226 for details on Command and Data loading):1. A: Load Command “0010 0000”.2. C: Load Data Low byte. Bit n = “0” programs the Lock bit.3. Give WR a negative pulse and wait for RDY/BSY to go high.The Lock Bits can only be cleared by executing Chip Erase.Reading the Fuse and LockBitsThe algorithm for reading the Fuse and Lock Bits is as follows (refer to “Programmingthe Flash” on page 226 for details on Command loading):1. A: Load Command “0000 0100”.2. Set OE to “0”, BS2 to “0”, and BS1 to “0”.
The status of the Fuse Low bits cannow be read at DATA (“0” means programmed).3. Set OE to “0”, BS2 to “1”, and BS1 to “1”. The status of the Fuse High bits cannow be read at DATA (“0” means programmed).4. Set OE to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock Bits can now beread at DATA (“0” means programmed).5. Set OE to “1”.Figure 108. Mapping Between BS1, BS2 and the Fuse- and Lock Bits During Read0Fuse low byteDATALock bits01Fuse high byte1BS1BS2230ATmega8(L)2486O–AVR–10/04ATmega8(L)Reading the Signature BytesThe algorithm for reading the Signature bytes is as follows (refer to “Programming theFlash” on page 226 for details on Command and Address loading):1. A: Load Command “0000 1000”.2. B: Load Address Low byte (0x00 - 0x02).3.
Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read atDATA.4. Set OE to “1”.Reading the Calibration ByteThe algorithm for reading the Calibration bytes is as follows (refer to “Programming theFlash” on page 226 for details on Command and Address loading):1. A: Load Command “0000 1000”.2. B: Load Address Low byte, (0x00 - 0x03).3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.4. Set OE to “1”.Parallel ProgrammingCharacteristicsFigure 109.
Parallel Programming Timing, Including some General TimingRequirementst XLWLt XHXLXTAL1t DVXHt XLDXData & Contol(DATA, XA0/1, BS1, BS2)t PLBXt BVPHPAGELt BVWLt WLBXt PHPLt WLWRWHt PLWLWLRLRDY/BSYt WLRHFigure 110. Parallel Programming Timing, Loading Sequence with TimingRequirements(1)LOAD ADDRESS(LOW BYTE)LOAD DATA LOAD DATA(HIGH BYTE)LOAD DATA(LOW BYTE)t XLXHtXLPHLOAD ADDRESS(LOW BYTE)tPLXHXTAL1BS1PAGELDATAADDR0 (Low Byte)DATA (Low Byte)DATA (High Byte)ADDR1 (Low Byte)XA0XA1Note:1.
The timing requirements shown in Figure 109 (i.e., tDVXH, tXHXL, and tXLDX) also applyto loading operation.2312486O–AVR–10/04Figure 111. Parallel Programming Timing, Reading Sequence (within the same Page)with Timing Requirements(1)LOAD ADDRESS(LOW BYTE)READ DATA(LOW BYTE)READ DATA(HIGH BYTE)LOAD ADDRESS(LOW BYTE)tXLOLXTAL1tBVDVBS1tOLDVOEtOHDZDATAADDR0 (Low Byte)ADDR1 (Low Byte)DATA (High Byte)DATA (Low Byte)XA0XA1Note:1. The timing requirements shown in Figure 109 (i.e., tDVXH, tXHXL, and tXLDX) also applyto reading operation.Table 95.
Parallel Programming Characteristics, VCC = 5V ± 10%232SymbolParameterMinVPPProgramming Enable Voltage11.5IPPProgramming Enable CurrenttDVXHData and Control Valid before XTAL1 High67nstXLXHXTAL1 Low to XTAL1 High200nstXHXLXTAL1 Pulse Width High150nstXLDXData and Control Hold after XTAL1 Low67nstXLWLXTAL1 Low to WR Low0nstXLPHXTAL1 Low to PAGEL high0nstPLXHPAGEL low to XTAL1 high150nstBVPHBS1 Valid before PAGEL High67nstPHPLPAGEL Pulse Width High150nstPLBXBS1 Hold after PAGEL Low67nstWLBXBS2/1 Hold after WR Low67nstPLWLPAGEL Low to WR Low67nstBVWLBS1 Valid to WR Low67nstWLWHWR Pulse Width Low150nstWLRLWR Low to RDY/BSY LowtWLRHWR Low to RDY/BSY High(1)(2)tWLRH_CEWR Low to RDY/BSY High for Chip ErasetXLOLXTAL1 Low to OE LowTypMaxUnits12.5V250µA01µs3.74.5ms7.59ms0nsATmega8(L)2486O–AVR–10/04ATmega8(L)Table 95.
Parallel Programming Characteristics, VCC = 5V ± 10% (Continued)SymbolParametertBVDVBS1 Valid to DATA validtOLDVtOHDZNotes:MinMaxUnits250nsOE Low to DATA Valid250nsOE High to DATA Tri-stated250ns0Typ1.tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write LockBits commands.2. tWLRH_CE is valid for the Chip Erase command.2332486O–AVR–10/04Serial DownloadingSerial Programming PinMappingBoth the Flash and EEPROM memory arrays can be programmed using the serial SPIbus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI(input) and MISO (output). After RESET is set low, the Programming Enable instructionneeds to be executed first before program/erase operations can be executed. NOTE, inTable 96 on page 234, the pin mapping for SPI programming is listed. Not all parts usethe SPI pins dedicated for the internal SPI interface.Table 96.
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