IS-GPS-200F (811524), страница 8
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The listof expanded P-code PRN assignments is identified in Table 3-Ib.The linear Gi(t) pattern (C/A-code) is the modulo-2 sum of two 1023-bit linear patterns, G1 and G2i. The lattersequence is selectively delayed by an integer number of chips to produce many different G(t) patterns (defined inTables 3-Ia and 3-Ib).The CM,i(t) pattern (L2 CM-code) is a linear pattern which is reset with a specified initial state every code count of10230 chips. Different initial states are used to generate different CM,i(t) patterns (defined in Tables 3-IIa and 3-IIb).The CL,i(t) pattern (L2 CL-code) is also a linear pattern but with a longer reset period of 767250 chips.
Differentinitial states are used to generate different CL,i(t) patterns (defined in Tables 3-IIa and 3-IIb).For a given SV ID, two different initial states are used to generate different CL,i(t) and CM,i(t) patterns.Section 6.3.7.1 provides a selected subset of additional P-, L2 CM-, L2 CL-, and the C/A-code sequences withassigned PRN numbers.21IS-GPS-200F21 Sep 2011The linear Gi(t) pattern (C/A-code) is the modulo-2 sum of two 1023-bit linear patterns, G1 and G2i. The lattersequence is selectively delayed by an integer number of chips to produce many different G(t) patterns (defined inTable 3-I).The CM,i(t) pattern (L2 CM-code) is a linear pattern which is reset with a specified initial state every code count of10230 chips. Different initial states are used to generate different CM,i(t) patterns (defined in Table 3-II).The CL,i(t) pattern (L2 CL-code) is also a linear pattern but with a longer reset period of 767250 chips.
Differentinitial states are used to generate different CL,i(t) patterns (defined in Table 3-II).For a given SV ID, two different initial states are used to generate different CL,i(t) and CM,i(t) patterns.Section 6.3.7.1 provides a selected subset of additional P-, L2 CM-, L2 CL-, and the C/A-code sequences withassigned PRN numbers.EPOCDETECTX1 EPOCHEPOCHRESET2050 HzZ-COUNT1 KHzZCOUNTERX1GENERATO1.023MHz10GOLD CODEGENERATOREPOCHDETECTX1(t)Gi(t)RESETCOMMANDGENERATORGi(t)RECLOCKINGDEVICED(t)FORMATTEDDATAX2i(t)Pi(t)REMOTCOMMANEPOCHRESETCODSELECDEVICX2GENERATO10.23 MHzFREQUENCYSOURCED(t)DATAENCODERPi(t)D(t)Pi(t)Figure 3-1. Generation of P-, C/A-Codes and Modulating Signals22IS-GPS-200F21 Sep 20113.3.2.2 P-Code Generation.
Each Pi(t) pattern is the modulo-2 sum of two extended patterns clocked at 10.23 Mbps(X1 and X2i). X1 itself is generated by the modulo-2 sum of the output of two 12-stage registers (X1A and X1B)short cycled to 4092 and 4093 chips respectively. When the X1A short cycles are counted to 3750, the X1 epoch isgenerated. The X1 epoch occurs every 1.5 seconds after 15,345,000 chips of the X1 pattern have been generated.The polynomials for X1A and X1B, as referenced to the shift register input, are:X1A: 1 + X6 + X8 + X11 + X12, andX1B: 1 + X1 + X2 + X5 + X8 + X9 + X10 + X11 + X12.Samples of the relationship between shift register taps and the exponents of the corresponding polynomial,referenced to the shift register input, are as shown in Figures 3-2, 3-3, 3-4 and 3-5.The state of each generator can be expressed as a code vector word which specifies the binary sequence constant ofeach register as follows: (a) the vector consists of the binary state of each stage of the register, (b) the stage 12 valueappears at the left followed by the values of the remaining states in order of descending stage numbers, and (c) theshift direction is from lower to higher stage number with stage 12 providing the current output.
This code vectorconvention represents the present output and 11 future outputs in sequence. Using this convention, at each X1epoch, the X1A shift register is initialized to code vector 001001001000 and the X1B shift register is initialized tocode vector 010101010100. The first chip of the X1A sequence and the first chip of the X1B sequence occursimultaneously in the first chip interval of any X1 period.The natural 4095 chip cycles of these generating sequences are shortened to cause precession of the X1B sequencewith respect to the X1A sequence during subsequent cycles of the X1A sequence in the X1 period. Re-initializationof the X1A shift register produces a 4092 chip sequence by omitting the last 3 chips (001) of the natural 4095 chipX1A sequence.
Re-initialization of the X1B shift register produces a 4093 chip sequence by omitting the last 2chips (01) of the natural 4095 chip X1B sequence. This results in the phase of the X1B sequence lagging by onechip for each X1A cycle in the X1 period.The X1 period is defined as the 3750 X1A cycles (15,345,000 chips) which is not an integer number of X1B cycles.To accommodate this situation, the X1B shift register is held in the final state (chip 4093) of its 3749th cycle. Itremains in this state until the X1A shift register completes its 3750th cycle (343 additional chips). The completion ofthe 3750th X1A cycle establishes the next X1 epoch which re-initializes both the X1A and X1B shift registersstarting a new X1 cycle.23IS-GPS-200F21 Sep 2011POLYNOMIAL X1A:1 + X 6 + X 8 + X 11 + X 12STAGENUMBERS01234567891011120001001001001234567INITIALCONDITIONS891011OUTPUT12TAPNUMBERSSHIFT DIRECTIONFigure 3-2.
X1A Shift Register Generator Configuration24IS-GPS-200F21 Sep 2011POLYNOMIAL X1B:125891011121+X +X +X +X +X +X +X +XSTAGENUMBERS01234567891011120010101010101234567INITIALCONDITIONS891011OUTPUT12TAPNUMBERSSHIFT DIRECTIONFigure 3-3. X1B Shift Register Generator Configuration25IS-GPS-200F21 Sep 2011POLYNOMIAL X2A:13457891011121+X +X +X +X +X +X +X +X +X +XSTAGENUMBERS01234567891011121010010010011234567INITIALCONDITIONS891011OUTPUT12TAPNUMBERSSHIFT DIRECTIONFigure 3-4. X2A Shift Register Generator Configuration26IS-GPS-200F21 Sep 2011POLYNOMIAL X2B:23489121+X +X +X +X +X +XSTAGENUMBERS123456789101112001010101010012345678INITIALCONDITIONS91011OUTPUT12TAPNUMBERSSHIFT DIRECTIONFigure 3-5.
X2B Shift Register Generator ConfigurationThe X2i sequences are generated by first producing an X2 sequence and then delaying it by a selected integernumber of chips, i, ranging from 1 to 37. Each of the X2i sequences is then modulo-2 added to the X1 sequencethereby producing up to 37 unique P(t) sequences.The X2A and X2B shift registers, used to generate X2, operate in a similar manner to the X1A and X1B shiftregisters.
They are short-cycled, X2A to 4092 and X2B to 4093, so that they have the same relative precession rateas the X1 shift registers. X2A epochs are counted to include 3750 cycles and X2B is held in the last state at 3749cycle until X2A completes its 3750th cycle. The polynomials for X2A and X2B, as referenced to the shift registerinput, are:X2A: 1 + X1 + X3 + X4 + X5 + X7 + X8 + X9 + X10 + X11 + X12, andX2B: 1 + X2 + X3 + X4 + X8 + X9 + X12.(The initialization vector for X2A is 100100100101 and for X2B is 010101010100).The X2A and X2B epochs are made to precess with respect to the X1A and X1B epochs by causing the X2 period tobe 37 chips longer than the X1 period. When the X2A is in the last state of its 3750th cycle and X2B is in the laststate of its 3749th cycle, their transitions to their respective initial states are delayed by 37 chip time durations.27IS-GPS-200F21 Sep 2011At the beginning of the GPS week, X1A, X1B, X2A and X2B shift registers are initialized to produce the first chipof the week.
The precession of the shift registers with respect to X1A continues until the last X1A period of theGPS week interval. During this particular X1A period, X1B, X2A and X2B are held when reaching the last state oftheir respective cycles until that X1A cycle is completed (see Table 3-VI). At this point, all four shift registers areinitialized and provide the first chip of the new week.Figure 3-6 shows a functional P-code mechanization for the 37 unique Pi(t) code phases, 1 ≤ i ≤ 37. 37 unique P(t)code phases. Signal component timing for these original P(t) code phases is shown in Figure 3-7, while the end-ofweek reset timing and the final code vector states are given in Tables 3-VI and 3-VII, respectively.28IS-GPS-200F21 Sep 201110.23 MHzX1EPOCHSET X1A EPOCHCRIREGISTER6121A4092DECODE6, 8, 11, 123750RESUMECLOCKCONTROLHALTZ-COUNTER403,200CI1SET X1BEPOCHRX1BREGISTER3749B127 DAYRESET4093DECODE1, 2, 5, 8,9, 10, 11, 12REGISTERINPUTSEND/WEEKCLOCKCONTROLHALTC - CLOCKI - INPUTR - RESET TOINITIALCONDITIONSON NEXTCLOCK3750CI1SET X2AEPOCHRX2AREGISTERC124092DECODE1, 3, 4, 5, 7,8, 9, 10, 11, 12START/WEEKRESUMEX2EPOCH37ENABLEAX1END/WEEKHALTPiBCLOCKCONTROLCIX2BREGISTER1 212RX2 iSET X2BEPOCH37491iC4093DECODE2, 3, 4,8, 9, 12X2SHIFTREGISTERFigure 3-6.
P-Code Generation29IS-GPS-200F21 Sep 2011012301230X1 EPOCHS37 Chips74 ChipsX2 EPOCHS *P EpochTIME01.5 sec3.0 sec4.5 sec7 days14 days* Does not include any offset due to PRN delay.Figure 3-7. P-Code Signal Component Timing30IS-GPS-200F21 Sep 2011Table 3-VI.P-Code Reset Timing(Last 400 µsec of 7-day period) **Code ChipX1A-CodeX1B-CodeX2A-CodeX2B-Code13451070967••••••••••••30233367••••••••••••312734714092••••••••••••4092409337494093409239894093••••••••••••4093409240934092** Last Chip of Week.** Does not include any X2 offset due to PRN delay.31IS-GPS-200F21 Sep 2011Table 3-VII.CodeX1AX1BX2AX2BFinal Code Vector StatesChip NumberVector State40914092409240934091409240924093100010010010000100100100100101010101001010101010111001001001110010010010000101010101001010101010Vector State for 1st Chipfollowing Epoch001001001000010101010100100100100101010101010100NOTE: First Chip in each sequence is output bit whose leading edge occurs simultaneously with the epoch.3.3.2.3 C/A-Code Generation.
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