Advanced global navigation satellite system receiver design (797918), страница 35
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This is the great advantage of using a code. T can therefore be interpreted as thetotal elapsed time over which that the signal is availableBut a practical DLL system the averaging time is extended by employing a loop of(one-sided) bandwidth BL which has an averaging time T = 1/2BL. Thereforeσ 2DLL =BL ∆2CN0C-42In our PSK systems presently set conservatively ∆ = 1 - however there is more to itthan that.In principle one can reduce D to achieve greater accuracy – but always assuming thatthe bandwidth W in the system is capable of supporting the necessary sharpness ofpulses (both transmitter and receiver).On a code demand basis – the same TC comparing PSK and BOC we can accept thatthe BOC system does demand an increased bandwidth and system bandwidthallocation.A fair comparison against PSK then allows that PSK system to improve its accuracyby reducing DC.8Comparison with digital loopThen standard theory finds for the input noiseσ 2v =η2δC-43Therefore to match a given C/N0 in the analogue r.f world choose A and σv such thatA= 2 × δ × Cσv N0 C-44C-9Analogue and digital DLL formulasC.9Time estimate error from the SLL^Equally we can in theory set τ = τ and consider variation of above as only between^τ* and τ within the SLLz IQI()τˆ * , τˆ = τ =ATGTG1~∫ s(t − τ) × s (t − τˆ )dt + TG0TG~∫ vI (t ) × s (t − τˆ )dtC-450ory IQI(τˆ , τˆ *)1(t) +TG=τ =A×()y IQI τˆ , τˆ * = τ = A ×TG~∫ vI (t ) × s (t − τˆ )dtC-460(t) + wIQIwhich allows evaluation of error exactly as if this was a simple correlation from DLL.This is easily evaluated directly from the correlation equations where s(t) is thesquarewave function as shown with the noiseless output belows(t)TS~s (t)C-10Analogue and digital DLL formulass(t)TScIQ(τ)τFigure C-1, Slope of output correlationdc 2 A=dτ TSC-47and noise output2wIQI=η2TC-48Therefore mean square timing jitter -normalised to sub-chip TS2σ SLL=Σ2TS2=1C-4928T A ηor in rf equivalent within a loop bandwidth BL2σ SLL=BL4CN0C-50C.10 Loop operationOn completion of one correlation (in time TG) the loop estimate of time delay isupdated.Simplify noise notation wk = wIQI[k]^^^τ *k+1 = τ *k + ( (τk − τ *k ) + wk ) × k0SC-51or in linear regionC-11Analogue and digital DLL formulas 2Aτˆ *k +1 = τˆ *k + × τ k − τˆ *k + wk k 0 S TS()C-52Let actual time delay τk = 0 then we are looking at an errorε k +1 = (1 − ρ )ε k + k 0 S wkC-53after definingρS =2A× k0STSC-54this is again a classic 1st order IIR filterThe mean square absolute timing error2Σ 2SLL = ε 2 =ρST 2× S × wIQI2 − ρS 2 A C-55or after normalising and identifying2σ 2SLL = ε 2 =ρSη 1 × ×2 − ρS 2 A 2TGC-56comparison of the various formulas then identifies an overall averaging time2 − ρSTG =ρS2−2 Ak 0S2 Ak 0STSTS TTG = S − 1TG Ak 0SC-57Substituting in (C-56) after inverting12σ SLL= 8× TA2× TG × S − 1η Ak 0SC-58Then standard theory finds for input noiseσ 2v =η2δC-59C-12Analogue and digital DLL formulasTherefore given in loop simulation A, σv, δ , TC, TG, k0S then12σ SLL= 4×A2σ v2×TG TS× − 1δ Ak 0SC-60C.11 Symbol list for Appendix C~s (t )orthogonal subcarrierAamplitudea(t)~a(t )b(t)Cdekockosmr(t)s(t)Ssin(Ω t)TCTGTSx(t)y(t)zΛΛVΩ~αlkGold code sequence a = + 1 or –1quasi orthogonal function obtained from subtracting so –called late gate from early gateBOC or LOC modulation product of a(t) and sub-carriercarrier powera data value ∈ (−1,+1)various kinds of signal processing errorDLL loop gainSLL loop gainsub-carrier frequency (Hz)LO referencesub-carrier sequence s = + 1 or –1‘squared up’ sub-carrier s(t)chip timecorrelation timesub chip timeincoming signal on carriersignal expressed as equivalent I and Qa correlation output obtained on completion of correlation timeidealised symbol to represent triangular output correlation shapeinvented symbol representing the quasi-differentiation of Λαlkδεnoise like cross correlation of competing Gold codes with referenceσvφφ'^φ^φ'τ^τ^*τω^ωω0sub-carrier frequency in rads/secnoise like cross correlation of competing Gold codes with orthogonal referencesampling intervaltiming error on a slope discriminationStandard deviation of additive white Gaussian noise to the received signala phase shift on that carrier By implication φ = φ(t) is time varying – but we do not showthis dependence for clarity.
The rate of change dφ/dt = ω is a Doppler shift.earlier or later phase shift in adjacent blocktest or trial phase shiftearlier or later phase shift estimate in adjacent blockthe delay time to be best estimated which is the navigational basic informationtest or trial delaytrial or test time delay on sub-carrierDoppler shift on carriertest or trial delay Doppler shiftthe nominal carrier frequency (actually down converted)C-13DSetting loop parameters in practiceIt is essential that GNSS receiver designers take into account the amplitudedependence of the different discriminators used in GNSS tracking loops. For thisreason a list of all common discriminator for PLLs, FLLs, SLLs and DLLs is given inChapter 5 and 6 of this thesis.
Looking at the SSTL SGR DLL loop can show a goodexample of the importance of these considerations. Table 5-3 shows the differentDLL loop discriminators for PSK signals.Table D-1, DLL discriminators for PSK signalsDiscriminatorCoherentDot productError signalDependencyeτ = wIQ × wIISlopeproportional(Decision-directed)≈ A2 × cos 2 φ − φˆ × VΛ (τˆ − τ ) × Λ (τˆ − τ )eτ = wIQ × sgn (wII )()≈ A × cos φ − φˆ × VΛ (τˆ − τ )IncoherentDot producteτ = wIQ × wII + wQI × wQQ≈ A2 × VΛ (τˆ − τ ) × Λ(τˆ − τ )Decision-directedeτ = wIQ × sgn (wII ) + wQQ × sgn (wQI )( ( )())≈ A × cos φ − φˆ + sin φ − φˆ × VΛ (τˆ − τ )Power22eτ = wIE2 + wQE− wIL2 − wQL2≈ A2 × VΛ (τˆ − τ )to A2Slopeproportionalto ASlopeproportionalto A2Slopeproportionalto ASlopeproportionalto A2The SGR DLL loop uses a dot-product discriminator, which imposes a very smallamount of loading on the receiver’s microprocessor but has an A2 dependence.
Theloop is first order with Doppler aiding from the carrier-tracking loop, which can bewritten as (repeat from Chapter 8)τˆ = τˆ + kφ × fφ + kτ × eτD–1wherekτ =K CD K DCO ∆T1D–2D-1Setting loop parameters in practiceT1 is the time constant of the first order loop, K CD is the gain of the codediscriminator and K DCO is the code DCO gain. The natural loop frequency ωn andloop bandwidth BL can then be calculated as follows.ωn =ωK FD × K DCO, BL = nT14D–3The value of K DCO is a constant mapping between the estimated delay error and therequired DCO frequency increment.
However, setting K CD is more complicateddesign issue. The normalised dot-product discriminator is shown in Figure 5-11, itdelivers a nearly true error between ±1/4 chip of code error. However, this is anormalised plot. In practice this error characteristic has an A2 dependence andtherefore expands and contracts with the power of the incoming signal.0.60.40.40.20.21.510.500.5101.5-0.20.2-0.40.41-40.6Code error (chips)0.5-200Phase error (rads)-0.524Code error (chips)-1Figure D-1, Dot product discriminator characteristicIt is desirable to avoid normalisation in the receiver tracking loops in order to reducemicroprocessor burden. A common practice is to design to loops for optimalperformance at the weakest C/N0 values to the receiver is likely to experience anddefine a range of operation through simulation.D-2Setting loop parameters in practiceFor example an early version of the SGR DLL was designed to give a loop bandwidthof 1Hz at a C/N0 = 40 dB-Hz or a signal to noise per correlation (1ms) of 10dB.Therefore, K CD is a constant set to achieve a true error at C/N0 = 40 dB-Hz.However, the discriminator error diverges from the true error above and below thispreset value.
This has the effect of increasing the effective loop bandwidth forstronger input signal values and decreasing the loop bandwidth for weaker inputsignal strengths. The effect of input signal strength on loop bandwidth and DLLtiming jitter is shown in Figure D-2.Figure D-2, SGR DLL loop bandwidth and timing jitter against input C/N0The changes to loop bandwidth with input C/N0 define limits to the range of reliablereceiver operation.
Figure D-3 shows the results of subjecting the SGR DLL toincreasing strong input signal levels. The timing jitter remain around 1m (predictedby Figure D-2), however at around C/N0 = 54 dB-Hz the loop begins to oscillategiving large timing errors (>50 m).D-3Pseudorange noise (m)Setting loop parameters in practice4002000-200-4000100200300400Time (sec)5006007000100200300500600700SNR (dB)252015400Figure D-3, SGR DLL pseudorange noise and receiver estimated SNR(dB-kHz)The above example shows the importance of DLL amplitude dependence, althoughthis issue is of equal importance to PLL, FLL and SLL designs. When using adiscriminator with any kind of amplitude dependence, extreme care must be taken bythe designer to insure the receiver will not be operating outside its reliable range.Clearly using normalised discriminators, which remove the amplitude dependence, isessential for high reliability application.
However, if the receiver hardware will notsupport this, loop designs with consideration of the receiver’s future environment ofoperation are required.D-4EChoosing a bump jumping thresholdGNSS BOC receivers operating the bump-jumping (BJ) algorithm must identify a BJthreshold. This threshold should be set high enough so that when the receiver istracking the central BOC correlation peak occasional noise induced increments of thevery early, VE or very late VL counters will never exceed this value. This wouldtrigger a false alarm and actually cause the receiver to action a jump away from thevalid tracking state.In order to determine this threshold we first followed the approach of [Fine andWilson 1999], assuming uncorrelated VE, P and VL correlations with randomGaussian noise on each on each correlation.
In order to identify our results with thispaper we consider in-phase correlations with a signal to noise per correlation ofS / N I = 10 dB and a BOC(2×fC, fC) signal (see Figure E-1).P rom pt gate1E arly gateLate gate1/2TSV L gateV E gate-3/4TCFigure E-1, BOC(2×fC, fC) false-lock example with BJ gatesThe Mathcad simulation program for uncorrelated noise samples is shown in FigureE-2.















