Advanced global navigation satellite system receiver design (797918), страница 37

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Initially we choose a rapidnoise update rate of fN = 61.38 MHz. This defines a decimation factor KN = 2 forfS = 122.76 MHz. Noise is updated every two samples of the time sequence. ThenC/N0 calculates here toCN0=2 122.76×× 10 6 = 76.7 × 10 3 Hz2240F–16or 48.8 dB-HzThis is actually rather a high value. We should be able to synthesis down to at least a‘representative minimum’ of say 38 dBHz, which is 10.8 dB down on this. And if wereally want to test performance of the receiver we shall need to go even lower. Withour current proposal this is no problem.

So for example with a reduced noise updaterate fN = 6.138 × 106 and therefore a decimation factor of 20 thenCN0=2 122.766.1386××10=2×× 10 6 = 7.67 × 10 3 Hz22204040F–17or 38.8 dB-HzF-5Digital Noise SynthesisEven lower update rate fN = 1.023 × 106 and therefore a decimation factor of KN =120finds thatCN0=2 122.761.023×× 10 6 = 2 ×× 10 6 = 1.28 × 103 Hz221204040F–18or 31.1 dB-HzIn this scenario then there are many options in setting the decimation value. ForKSC = 120 then possible valuesKN = ( 2, 3, 4, 5, 6, 8, 10, 12,15, 20, 30, 40, 60, 120)If we want to go even lower than this then the algorithm needs to be modified so thatthe noise update rate is slower than the code rate.F.6Spectral analysisSpectral analysis at the highest proposed noise update rate fN = 61.38 MHz shows apronounced ‘skew’ of the power density - which does not peak where we want it(although the spot value is correct).operatingfrequency1.51oG( ω )0.500.511.522.533.54ω2⋅ πFigure F-2, Power spectrum with ND = 2 noise decimationThe function being plotted isF-6Digital Noise Synthesis  ωT  2  sin  0 4   2G (ω) = 2σ T0   ωT04(2F–19)where here 1/T0 = 61.38 MHzThere seems little point in trying to improve on this since the correlation action in thereceiver effectively applies a narrow band filter in the order of kHz.

In any case withhigher decimation factors the spectrum increasingly centralises. For example with anincrease to KN = 4 the spectrum has already shifted appropriately:0.871operatingfrequency1oG( ω ) 0.5000.511.522.53ω03.543.9952 ⋅πFigure F-3, Power spectrum with ND = 4 noise decimationThe proposed digital simulation will provide for a highly accurate testing of receiverperformance since the noise level is precisely specified.F.7PSK analysisThe aim is to add a precisely controlled amount of noise to otherwise ‘clean’ benchgenerated GPS signal modulating an IF of 61.38 MHz.The following analysis is first expressed in terms of standard L1 C/A code GPS.Consider first a digital baseband construction – called a unit amplitude a[ ] sequencein the appendix - scaled up to an amplitude A.

There are 1023 chips following theprescribed code rule in interval T = 1 ms.F-7Digital Noise SynthesisIn the modulator, from a[ ] form a what we call a b[ ] sequence which – in the absenceof noise - consists of 120 repeated samples of each chip. The sample rate fS = 122.76MHz. To form an IF sequence c[ ] at 61.38 MHz is simply a matter of alternating thesample sequence b[ ].The digital noise synthesis consists of adding independent random samples u[ ] ofsynthesised Gaussian noise to the A × b[ ] sequence.

The perceived difficulty for ascheme of fixed sample rate is the difficulty in realising a sufficiently high level ofnoise. In a digital realisation in amplitude is that minimum signal amplitude isnecessary A = 1 while a typical maximum σ = 40 (allowing Gaussian noise in a range± 3σ over 8 bit representation ±128.Independent noise of r.m.s. value σ could be added on every sample at ratefN = 122.76. MHz. to every term in A ×b[ ].We can however lower the update rate of noise in the range downward tofN = 1.023 MHz by allowed multiples.This has the effect of increasing the effective noise level after demodulationNow consider a de-modulation stage where the c[ ] is sign alternated back to b[ ] andenvisage a correlation stage clocked at 61.38 kHz which processes all the samplesIn the case of perfect lock and no noise sequence A × b[ ] can be recovered will lineup with a unit replica bR|[ ] = b[ ].

Envisage running a correlation over 1 periodicinterval T = 1 msec. In this somewhat impractical scenario there will be a total ofN = 1023 × 120 = 122760 terms to be summed as inΛ[0] =ANN −1∑ b[k ]bR [k ] = AF–200In a correlation time T there are fN T independent noise samplesthe achieved signal to noise after correlation depends on the number of independentnoise samples within that interval T.It is easily argued that achieved signal to noiseγ2 =A2σ2×T × fNF–21F-8Digital Noise Synthesiswhich is maximum on fN = 122.76 MHz when fN T = 122,760 and is a minimum onfN = 1.023 MHz when fN T =1023.This gives us a noise range over 120 : 1 . We may note that this is a purely digitalargument. This result can be generalized to an extended correlation time TL definedby a loop response to read2γ =A2σ2× TL × f NF–22Comparing then against a standard formula for GPS base band signal in presence ofanalogue low pass (white approximation) of one-sided density ηγ2 = 2×A2× TLηF–23It can be shown then for a phase locked I channel that equivalentlyγ2 = 2×C× TLN0F–24where C is the carrier power before demodulation and N0 is the band-pass one sidednoise density(white approximation).

Therefore we have synthesised a noise channelwhere2 A2 f NC=N0σ2F.8F–25Extension to BOC analysisA similar argument finds that one can use exactly the same formulas provided anappropriate restriction on range on fN is observed. It is necessary to have at least oneindependent noise sample per sub-chip which restricts how low one can go with fN.F-9Digital Noise SynthesisExample BOC(1,1). Here there are two sub-chips within in one chip of 1/1.023 µs.Therefore lowest allowed value to fN = 2.046 MHz. Highest value is stillfN = 122.76 MHz. In spectral terms a ‘sub-chip’ pulse of noise covers the range ±2.046 and therefore satisfactorily covers the two main lobes.4030SS ( f)20SN( f)10432101234fFigure F-4, Spectral plots of BOC(1, 1) signal (red) and digital noise (blue)fS = 1 MHz, fC = 1 MHz, fN = 2 MHzExample BOC(10,5).

Lowest allowed fN = subchip rate = 20.46 MHz. Highest valueis still fN = 122.76 MHz. In spectral terms a ‘sub-chip’ pulse of noise covers the range± 20.46 MHz and therefore satisfactorily covers the two main lobes.4030SS ( f)20SN( f)1020151050510152025fFigure F-5, Spectral plots of BOC(10, 5) signal (red) and digital noise (blue)fS = 10 MHz, fC = 5 MHz, fN = 20 MHzF-10G FPGA Correlator RegistersRegister nameDescriptionSystem registersPROG_ACCUM_INTContains a count value for generating the interrupt for theprocessor to read the accumulation data (nominally 854us)PROG_TIC_HIGHContains the higher 16-bits of the TIC count value (nominally 0.1s)PROG_TIC_LOWContains the lower 16-bits of the TIC count value (nominally 0.1s)TEST_CONTROLEnablesACCUM_STATUS_AContains flags telling the processor new accumulation data is readyfor each tracking channelINPUT_SIGNALContains samples of the input signal for AGC and noise testingChannel registers (read)CODE_DCO_PHASEContains the fractional part of the code phase measuredsynchronised with the TIC from the code DCOCODE_PHASEContains the half chips of the code phase measured synchronisedwith the TICCARRIER_DCO_PHASEContains the fractional part of the carrier phase measuredsynchronised with the TIC from the carrier DCOCARRIER_CYCLE_LOWContains the lower 16-bits of the carrier cycle count in a singleTICCARRIER_CYCLE_HIGHContains the higher 16-bits of the carrier cycle count in a singleTICSUB_DCO_PHASEContains the fractional part of the sub-carrier phase measuredsynchronised with the TIC from the sub-carrier DCOSUB_CYCLE_LOWContains the lower 16-bits of the sub-carrier cycle count in a singleTICSUB_CYCLE_HIGHContains the higher 16-bits of the sub-carrier cycle count in asingle TICw_III_LOWContains the lower 16-bits of the wIII correlationw_III_HIGHContains the higher 16-bits of the wIII correlationw_IIE_LOWContains the lower 16-bits of the wIIE correlationw_IIE_HIGHContains the higher 16-bits of the wIIE correlationw_IQI_LOWContains the lower 16-bits of the wIQI correlationw_IQI_HIGHContains the higher 16-bits of the wIQI correlationw_QIE_LOWContains the lower 16-bits of the wQIE correlationw_QIE_HIGHContains the higher 16-bits of the wQIE correlationw_QII_LOWContains the lower 16-bits of the wQII correlationw_QII_HIGHContains the higher 16-bits of the wQII correlationG-1FPGA Correlator Registersw_IIL_LOWContains the lower 16-bits of the wIIL correlationw_IIL_HIGHContains the higher 16-bits of the wIIL correlationw_QQI_LOWContains the lower 16-bits of the wQQI correlationw_QQI_HIGHContains the higher 16-bits of the wQQI correlationw_QIL_LOWContains the lower 16-bits of the wQIL correlationw_QIL_HIGHContains the higher 16-bits of the wQIL correlationChannel registers (write)SATCNTLSelects which satellite the individual channel tracks and alsoselects different tracking modesCARRIER_DCO_INCR_HIGHSelects the higher 16-bits of the carrier DCO increment per sampleclock periodCARRIER_DCO_INCR_LOWSelects the lower 16-bits of the carrier DCO increment per sampleclock periodCODE_DCO_INCR_HIGHSelects the higher 16-bits of the code DCO increment per sampleclock periodCODE_DCO_INCR_LOWSelects the lower 16-bits of the code DCO increment per sampleclock periodCODE_SLEW_COUNTERSelects the code slew the user wish to impart on the replica signalin half chipsSUB_DCO_INCR_HIGHSelects the higher 16-bits of the sub-carrier DCO increment persample clock periodSUB_DCO_INCR_LOWSelects the lower 16-bits of the sub-carrier DCO increment persample clock periodG-2HDerivation of exact timing formulas for sine andcosine BOCThis appendix was kindly supplied by Dr Hodgart and provides the derivation oftiming jitter of both sine BOC (sBOC) and cosine BOC (cBOC) modulations.H.1Direct analysis for sBOC(1,1)Identify chip width TC , sub-chip width TSp(t)ATSh(t)1TS∆q(t)+ ∆v(t)q(t)+ v(t)+++−TCTDwhite noise u(t)Figure H-1, Delay line subtractor for sBOC(1,1)main peak noiseless output q(0) = 2Aat displacement T output q(TS) = −AInitially choose delay line subtractor also TD = TSTherefore maximum positive and negative peak in ∆q(t) = ± 3ASlope in ∆q(t) = 6A/TSEquivalent difference impulse response∆h(t ) = h(t ) − h(t − TS )H–1Then noise out∆v 2 =()ηη 1 2η 6∆h(t )2 dt =1 + 2 2 + 12 =∫22 TS2 TSH–2therefore mean square noise jitter for just one pulse (duration TC)2η 6  TS η TΣ = ×× = × S22 TS  6 A 2 6A2H–3H-1Derivation of exact timing formulas for sine and cosine BOCThis is reduced in a loop system of effective integration time TL toΣ2 →η TS TC××2 6 A 2 TLH–4One can show that A2/η = C/N0 in a phase synchronised I-channel.

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