Arthur Sherman - Chemical Vapor Deposition for Microelectronics (779637), страница 15
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Theinfluence of temperature and pressure on deposition over many wafers in a tubefurnace 3 is shown in Figure 12. Clearly, uniform wafer-to-wafer depositionscan be achieved by modifying the reactor temperature along the reactor axis.Although deposition rates are higher at the higher pressures (700 mTorr), thewithin-wafer uniformity is not as good, so depositions tend to be done at 500mTorr. When pure SiH 4 is used, extreme sensitivity to SiH 4 flow is found, asillustrated in Figure 13. In addition, the deposition rate is reduced from 200A/min with 23% SiH 4 to 125 A/min with 100% SiH 4 .2.0a1.6..-----..FLOW - 650 sceMSiH4 - 23%PRESS - 0.5 TORR TIME - 30 MIN~(J)(J)~~ 1.2~~~o~~>..J0.8, .
_ ..0- --~o-.-.~o0.--- ---'"_.-0--_ -.-.- . >-.-.-.- --0---.-0... ......0.4\'675°C-0 6470CIra 642°f... •... 619.......60· •8Q1561624324048WAFER POSITION (3/8" SPACING)0.6 r-----.---~--.__-__r--__.__---,-----,FLOW -.55CJ)f3Z~J:I-650 SCCMSiH4 - 23%TEMP - 643-649°Ct - 26 MIN-+---1------+------'--------1(0.7 TORR)... .AA •••• • ••••A • • • • • • • 6 • • • • • • • • • • • • • • • • <4"0.5 ~---+---_+_-__+---+---+__---+-----1(0.5 TORR)L.45 ~--+-----+----+---+----:::;----~l==-·--t-----i~0.0.4 1------+----+-_--0- _0---o-0-(0.3TORR)__ .0--0;.--.0--20406080100120WAFER POSITION (3/16" SPACING)Figure 12: Poly thickness profiles. 3140Thermal CVD of Dielectrics and Semiconductors79SiH4(SCCM)I.55 I----+-----+----+-----+-<t/:r---+-----::O"O-isP - 0.6 TORR.501----+-----+----+-----__/_- T _ 607-629-654°Ct - 45 MIN.N2- 0en~Z.451----+-----!'~---+----+----+-----+--;~"tfo-i:.-..47>-Jo0.4040206080100120WAFER POSITION (3/16" SPACING)Figure 1:3: Poly thickness profiles for 100% SiH 4 .
3So far, we have ignored the primary reason poly films are used in integrated circuits. Heavily-doped poly is used as a gate electrode, and the electrical conductivity of this material is of prime importance. Therefore, we haveto inquire into the feasibility of doping poly as it is being deposited by CVD.The obvious approach to this problem would be to deposit from a SiH 4 +PH 3 mixture, in the hopes that a sufficient quantity of P dopant could be incorporated into the poly. Many attempts to do this have been unsuccessful.For example, depositions at 623°C and 100 mTorr were carried out with 30sccm of SiH 4 and 0.75 sccm of PH 3 •10 Without the PH 3 , deposition across asingle wafer was very uniform (see Figure 14). Adding the small quantity ofPH 3 reduced the deposition rate at the wafer center by 20:1, and yielded a nonuniform film.' ; 200 r-----,.----r--r---,--~-r_____r----r---r--_~"'U1~A100cmo000 0 0 0 000OCIJ]oa::I-~40Z«..........w~n:::II~oa::o20100%0-1.00B00000000-0.500.50~1.0POSITION RELATIVE WAFER CENTER (INCHES)Figure 14: Deposition rate profile across a wafer in LPCVD silicon deposition.
1oReprinted by permission of the publisher, The Electrochemical Society, Inc.80Chemical Vapor Deposition for MicroelectronicsThere are two issues that have to be resolved when reviewing these results. One-why is the deposition rate reduced by such a large factor? Second-why is the deposition nonuniform now, when it was uniform withoutthe PH 3 ? The explanation proposed 10 for the first question is that PH 3 preferentially adsorbs on the silicon surface, preventing SiH 4 from adsorbing andsubsequently decomposing to Si and H 2 •The explanation for the second question is somewhat more involved.It is suggested that deposition occurs both as a result of Si H4 decomposition onthe surface (heterogeneous reaction), and Si H 4 decomposition in the gas phase(homogeneous reaction) to Si H 2 and H 2 and subsequent deposition by Si H 2reaching the surface.
Because SiH 2 is a free radical, it should react at the surfacewith unit probability. This would have the effect of depleting the SiH 2 from thegas phase, and return the process to one controlled by diffusion rather thansurface kinetics. Therefore, a thinner poly film at the wafer center is a reasonable expectation.Because of the above-mentioned difficulties in trying to dope poly withphosphorus in situ, such films have traditionally been deposited undoped.Doping can then be accompl ished by ion implantation or diffusion.3.4.2 Electrical Resistivity of Doped FilmsRegardless of the method of doping the LPCVD poly film (in situ, implantor diffusion), the important fact is that the resistivity of the film is higher than adoped epi film would be. 11 Resistivity measurements are shown in Figure 15 forboth phosphorsus and boron doping.
For low doping concentrations, the resistivity can be five orders of magnitude higher. Even at higher concentrations, westill see an order of magnitude greater resistivity.o0POLYoo PHQS. DOPED, I070 ePHOS. DOPED, U700e0b. BORON DOPED, 1070 eo0 b.~o3= 10~VlVl~1EPI~~Figure 15: Resistivity versus doping concentration. 11 Reprinted by permissionof the publisher, The Electrochemical Society, Inc.Thermal CVD of Dielectrics and Semiconductors81It is fairly obvious that this phenomena must be related to the fact that thepoly is made up of many small grains with their attendent grain boundaries.Each grain is a single crystal and should behave as the epi films do. Therefore,the cause of the increased resistivity must involve the grain boundaries.There are two proposals as to why grain boundaries should effect theelectrical properties of doped poly films.
One is that dopant atoms segregate atthe grain boundaries where they are electrically inactive,t2 thereby reducing thedopant concentration in the grains themselves. For lightly-doped films, most ofthe dopant segregates at the grain boundaries. At higher dopant levels, the grainboundaries become saturated and the rernaining dopant goes directly into thegrains. Thus, heavily-doped poly films approach doped epi films as far as resistivity is concerned.The second argument states that since the atoms in the grain boundaries aredisordered, incomplete atomic bonding could lead to the formation of trappingstates. Such trapping states then could immobil ize carriers, and so reduce thenumber of free carriers available to conduct electricity.13 Once the mobilecarriers are trapped, the grain boundaries become electrically charged, creating apotentia I barrier to the flo\,'V of carriers from one crysta I to another.Undoubtedly, both explanations play some role, since each has someexperimental verification to support it.
It will depend on the type of dopant, theextent of dopant, and grain size. As noted earlier in Chapter 2, poly grains willgrow larger when the film is doped, as well as annealed at a high temperature fora reasonable length of time.In support of a dual mechanism, recent experimental evidence 14 has shownthat a significant fraction of arsenic and phosphorus dopants may appear at grainboundaries, especially for moderate dopant concentrations. The fraction segregating to the grain boundaries is found to be inversely proportional to the size ofthe grains. For boron-doped films, no evidence was found of dopant segregationat the grain boundaries.3.5 EPITAXIAL SILICONIn the previous section, we discussed the CVD of silicon thin films.
For thepressures and temperatures at which those depositions were carried out, thefilms were polycrystalline. If the depositions had been carried out at highertemperatures, single-crystal (epitaxial) films would have been possible. In thissection, we will discuss some of the factors that govern the growth of epi siliconfilms.Early attempts to build integrated circuits on single-crystal wafers cutfrom single-crystal boules met with many difficulties due to the high concentration of impurities present.
A sol ution to th is practical problem was found bygrowing epitaxial (epi) silicon by CVD on top of the impure wafers. Since thefeedstock gases used in the epi process (dichlorosilanes mixed with hydrogen)could be highly purified, the resulting epi films were much purer than theunderlying substrate. It was in this very pure epi film (so-called "device quality"silicon) that high-quality integrated circuits could be built. The single-crystalwafer became, in effect, just a mechanical holder for the epi film (of course,one with the correct crystal structure).82Chemical Vapor Deposition for MicroelectronicsIn the early integrated circuit developments, the epi layers were generallyquite thick A typical layer could be 20 microns thick. Therefore, high deposition rates were essential to the economic viability of the equipment.
The highest deposition rates are possible with atmospheric pressure reactors at hightemperatures. As discussed in Chapter 1, the higher temperature depositionstend to be diffusion controlled, and this ruled out hot tube systems with manywafers in a single batch. Accordingly, the industry standard has been the coldwall batch reactor (barrel type) run at atmospheric pressure. Some systemsare being operated at 80 Torr, but this is still in the diffusion-controlled regime.Some of the specifics of the epi silicon CVD process will be covered inthe balance of this chapter.3.5.1 The CVD Process for Epi SiliconThe reactions that have been used to create epi silicon films commerciallyinvolve the H 2 reduction of the chlorosilanes.
As we learned earlier in Chapter1 in studying the equilibrium behavior of the H-CI-Si system, we can depositsolid silicon from SiCI 4 + H 2 , SiCI 3 H, or SiCI 2 H 2 - Also, H 2 can be added to thelatter two, if desired. Obviously, silicon will also deposit from SiH 4 .
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