Roland A. - PVD for microelectronics (779636), страница 45
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The wafer is then transferredto another chamber (see Fig. 7.15) where high-pressure Ar is isostaticallyapplied at moderate temperature to force the Al into the hole by an enhanced plastic flow process. Assuming that all of atoms from the sputtering ambient enclosed in the hole dissolve into the Al, this would representonly an insignificant impurity in the filled plug ( = 0. I ppm Ar). The elevated temperature is employed to reduce the flow stress needed to achieveplastic deformation. I t is also reported that that elevated temperature promotes a dynamic recrystallization, leading to strain-free grains with verylarge median grain size (= 10 p m compared to 2 p m for TSP-processedR. POWELL AND S.
M. ROSSNAGEL236FIG. 7.14Schematic of the Forcefill TM process applied for AI via filling.A1), which could contribute to increased electromigration resistance[7.20]. The relative contributions of temperature and pressure to fill capability are illustrated in Fig. 7.16, which shows how one can fill at lowerprocess temperature by applying higher pressure.It has been reported that Forcefill AI provides global, complete filling ofboth straight-walled and reentrant 0.5-/~m holes provided the metal is sufficiently thick on the field (e.g., 700 nm) to bridge the diameter of the holeand form an encapsulated void.
That is, the fill capability of the method isless dependent on the amount of sputtered AI that reaches the bottom andsidewalls of the hole than on the amount deposited on the field. Since theformer coverage depends on aspect ratio and the latter coverage does not,Forcefill is well suited for global filling even when features of different aspect ratio are present on the wafer surface. The method has been applied to64Mb DRAMs and multilevel 0.35-/~m logic devices.PLANARIZED PVD: USE OF ELEVATED TEMPERATURE AND/OR HIGH PRESSURE237FIG.
7.15 Schematic of the high pressure chamber used as part of the Forcefill TM process. Two radiant heaters are used for heating the wafer ( ~ 400~during the application of ultrahigh isostaticpressure ( ~ 60 MPa). (Source: G. Dixet et al, Semiconductor Int'l., p. 79, August 1995).On the other hand, concerns have been raised about the compatibility ofextremely high pressure with deformable, organic interlayer dielectrics.Also, while a reduced thermal budget is expected for Forcefill over reflow,it may not be significantly better than that of TSP since both utilize comparable temperature ( ~ 400~and times. It has also been reported thatdeep grain boundaries can form in AI films when the Forcefill process iscarried out over densely packed arrays of vias [7.23]. Such films have acracked appearance where AI grains have separated from one another,which could lead to reliability or manufacturing difficulties if not controlled.
The effect has been attributed to the fact that in such closelypacked arrays, a single A1 grain can serve as the source of material to fillseveral underlying vias. During high-pressure annealing, a large fraction ofthe grain's volume ( > 25%) is rapidly consumed, which forces it to distortand physically separate from neighboring grains [7.23].Forcefill shares elements in common with both reflow and TSP hot processing. For example, Forcefill and reflow both utilize a conformal PVDbarrier/liner and a PVD A1 step followed by transfer under high vacuum toa separate module where heat treatment is carried out. Of course, the ultrahigh pressure used results in a radically different module (Fig.
7.15).Both the Forcefill and the TSP processes have a common interest in buriedvoids, although Forcefill is designed to induce their formation while TSPR. POWELL AND S. M. ROSSNAGEL238430 ~[iA(JI~....'...........i..................i.......II 6.50 llm, 3: I~AR Holes ......i0.351~m, 4 : l A R H o l e s i*=Ot'i................~.iQL.410400 --r'i...................~....."'~........i............i..................-..................i..................~.................-..................!Ib,390ii-!................ "380i .................. ~ .................. ~.............. ,~O(9::3(g4)O.EF--"~i!~'! ..................
i .......... ~~"!ii......i ..................i .................. !................ ~ .................. ~..................t ................. ~ ..................4)Im0~3r~3eo40iiiii'"~.i.!. . . . . . . . . . . . . . . . . . . . . . .I0.3....I0.4...I0.5....i0.6....I0.7i0.8i0.9iii1.0I1.1! .................. !Relative PressureFIG.
7.16 The ability to completely fill a feature (void-free filling) using the Forcefill T M processdepends on both pressure and temperature, as illustrated for a 0.5-/xm, 3:1 aspect ratio hole (Source:G. Dixit et al, Semiconductor Int'l., p. 79, August 1995).seeks to p r e v e n t this. Also, both m e t h o d s have been used for void-free filling of sub-0.5-/xm features at 4 0 0 ~ and thus offer a l o w e r - t e m p e r a t u r eprocess alternative to reflow.7.5 ConclusionsAs d i s c u s s e d above, elevated t e m p e r a t u r e and ultrahigh pressure havebeen used to p r o m o t e material transport both during and after PVD.I m p r o v e m e n t s to these m e t h o d s e.g., h i g h e r v a c u u m base pressure, improved w e t t i n g / n u c l e a t i o n layers, m o r e c o n f o r m a l cold layers for cold-hotp r o c e s s i n g - have a l l o w e d P V D to be applied for coating and filling of0.25-/xm U L S I structures.
In spite of this success, it m a y not be possible toextend the s a m e m e t h o d s to deep s u b m i c r o n devices (-< 0 . 1 8 / x m ) due toreduced t h e r m a l budgets, m u c h higher aspect ratios (e.g., s i m u l t a n e o u sfilling of a 5:1 via and 5:1 trench with the d u a l - d a m a s c e n e process is effectively like filling a 10:1 aspect ratio feature), and the i n t r o d u c t i o n ofPLANARIZED PVD: USE OF ELEVATED TEMPERATURE AND/OR HIGH PRESSURE239interconnects and via plugs based on Cu which, compared to A1 at a giventemperature, has much smaller surface and bulk self-diffusion coefficients. Of the methods described above, the conventional reflow processis least likely to be deployed for 0.18-/xm devices due to the relativelyhigh temperatures and need to customize geometry (e.g., sloped or champagne-glass-shaped contacts).
Likewise, the Forcefill method may not becompatible with temperature- and pressure-sensitive low-k polymers norwork as well with Cu as with A1. The most likely scenario for filling appears to be the use of slightly elevated temperature (--< 400~PVD insynergistic combination with ionized PVD or CVD (see Section 9.9). Forexample, a Ti or TiN wetting layer with improved conformality could bedeposited using ionized PVD, the structure partially filled using CVD A1,and then filling and surface planarization completed using hot PVD A1Cuin which the elevated temperature (or a subsequent anneal) serves to driveCu from the A1Cu into the underlying A1 film for improved electromigration resistance.References7.1.
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Pramanik and A. N. Saxena, "Aluminum metallization for ULSI,'" Solid State Tech. 73-79(Mar. 1990).7.8. P. Singer, "Low k Dielectrics: The search continues," Semicond. Int., 88-96 (May 1996).7.9. K. Kikuta, N. Itoh, and T. Kikkawa, "Low temperature aluminum reflow sputtering," in Proc.Tech. Syrup. of SEMICON-Korea, pp. 281-287 (Nov. 9-10, 1993).7. !0. B.
Zhao, M. A. Biberger, V. Hoffman, S.-Q. Wang, P. K. Vasudev, and T. E. Seidel, "A novellow temperature PVD planarized AI-Cu process tor high aspect ratio sub-half micron interconnect,'" Proc. Int. Electron Devices Meeting, IEEE, New York) pp. 353-356 (1996).7. Ii.
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M. ROSSNAGEL7.13. K. Kikuta, Y. Hayashi, T. Nakajima, K. Harashima, and T. Kikkawa, "Aluminum-germaniumcopper multilevel damascene process using low-temperature reflow sputtering and chemicalmechanical polishing," IEEE Trans. on Electron Devices 43(5): 739-745 (1996).7.14. K. Kikuta, "AI damascene technology for multilevel interconnections," Technical Digest of theIEDMS Meeting, Taiwan, December 16-20, 1996), abstract A4-3, pp.
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