Лекция 4 - MIPS_1 (1162607)

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MIPS ProcessorRegisters in MIPS• In MIPS, there are 32 Registers.• We need read up to two registers, andwrite to up to one register.• Think registers as D flip-flops. Eachregister has 32 Dffs.• The control signals are:– readReg1, readReg2: 5 bits. Used to specifywhich reg to read.– writeReg: 5-bits. Used to specify which reg towrite.– Data: if write, what data should be written intothe reg.– RegWrite: whether to write or not.• This is for read.To write to a register• The data is connected to every register.• Use RegWrite, generate a ``LOAD’’ signal forthe register you want to write to.Every register has a LOAD signal.

If thatsignal is `1’, new data will be set. Only the target register’s LOAD signal is`1’.RAMA RAM Example• RAM. Control signals:– address: If write, which locationto write to. If read, which locationto read from.– Chip select: whether to use thischip or not.– Output enable: whether toenable output (output somevoltage or in high-impedencestate)– Write enable: whether to read orwrite.– Din: if write, what data should bewritten into the location specifiedby address.11/8/2007 10:04:17 AM•week11-5.pptAssume that there is a RAM withonly 2 address lines and two bitdata lines. How many bits can ithold?6The processor• We now know all the parts in the processor.– ALU– PC– Register fileAlso– RAM• How to put them together? How to makethem execute an instruction as we need?ALUThe execution of an instruction• First we need to fetch the instruction at theaddress given by the current PC frominstruction memory• Then we need to decode the instruction• Based on the instruction, we need to doaccordingly• For sequential instructions, we then go thenext instruction by increasing the PC.

For jumpand branch instructions, PC will be changedBasic MIPS Implementation• We will focus on design of a basic MIPSprocessor that includes a subset of the coreMIPS instruction set– The arithmetic-logic instructions add, sub, and, or,and slt– The memory-reference instructions load word andstore word– The instructions branch equal and jump11/18/2007 7:39:36 PMweek13-1.ppt10MIPS Implementation Overview• For every instruction, the first two steps are identical– Fetch the instruction from the memory according to thevalue of the program counter– Read one or two registers (using fields of instructions toselect the registers)• For load word, we need to read only one register• Most other instructions (except jump) require we read tworegisters– After the two steps, the actions required depend on theinstructions• However, the actions are similar11/18/2007 7:39:36 PMweek13-1.ppt12Instruction Fetch and PC Increment• Since for every instruction, the first step is to fetchthe instruction from memory– In addition, for most instructions, the next instruction willbe at PC + 411/18/2007 7:39:38 PMweek13-1.ppt13R-type Instructions• Also called arithmetic-logical instructions– Including add, sub, and, or, and slt– Each one reads from two registers, performs anarithmetic or logical operation on the registers,and then write the result to a register11/18/2007 7:39:38 PMweek13-1.ppt14R-type Instructions• Suppose the instruction is add $t0, $t1,$t2, what are the read reg1, read reg2, and writereg? What is the value of RegWrite? How to controlthe ALU to do add?11/15/2007 5:02:08 PMweek-13-3.ppt15Datapath only for R-type instructionsDatapath only for R-type instructions(Answer)Data Transfer Instructions• Load word and store word instructions havethe following general form– lw $rt, offset_value($rs)• opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)– sw $rt, offset_value($rs)• opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)– They need to compute a memory address byadding the base register to the sign-extended 16bit offset11/15/2007 5:02:10 PMweek-13-3.ppt18Load• For instruction load $t0, 16($t1),what should the control signal be?Data pathData path only for lw (answer)Data path only for sw (answer)Branch Instruction• Beq has three operands, two registers that arecompared for equality and a 16-bit offset usedto compute the branch-target address– beq $rs, $rt, offset• opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)– Note that the 16-bit offset is given in terms ofinstructions, not bytes and is relative to PC + 411/18/2007 7:39:42 PMweek13-1.ppt23Designing a processor only for beqAre these enough? How many adders do we need? How to do the selection?Designing a processor only for beqDesigning a processor only for beq(answer)11/18/2007 7:39:43 PMweek13-1.ppt26In class exercise• Design a simplified MIPS processor that supports only addi.

Assumethe control signals have been generated and only the data path needs tobe designed.addi $rt, $rs, immopcode (6 bits) rs (5 bits) rt (5 bits) imm (16 bits).

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