Wiley.Symbian.OS.Internals.Real.time.Kernel.Programming.Dec.2005.eBook-DDU (Symbian Books), страница 10

Writes of new pixel data will gaina small speed-up because of the write buffer, and read–modify–writeoperations will be aided by the cache. But running all of Symbian OS ina write-through cached system reduces performance by over 30%.To make full use of the DCache for writes as well as reads, SymbianOS uses a scheme called copy-back.

Write hits into the cache remain inthe cache, where they may be overwritten again. Copy-back results in amassive reduction of write traffic to memory by only writing data when itis evicted.Cache lines that have been modified are tagged by dirty bits – normallytwo of them for a pair of half lines. When it is time to evict the cacheline, the dirty bits are evaluated, and dirty half lines are written backout to memory through the write buffer. Half lines are used to reducethe write bandwidth overhead of unmodified data, since clean data canbe discarded.Flushing the entire contents of a copy-back cache will take somemilliseconds, as it may be populated entirely with dirty data.2.3 Random Access Memory (RAM)Random Access Memory (RAM) is the home of all the live data within thesystem, and often the executing code.

The quantity of RAM determinesthe type and number of applications you can run simultaneously, theaccess speed of the RAM contributes to their performance.A Symbian OS phone will have between 8 and 64 MB of RAM. TheOS itself has modest needs and the total requirement is determined by theexpected use cases. Multimedia uses lots of RAM for mega-pixel cameras30HARDWARE FOR SYMBIAN OSimages and video recording. If NAND Flash memory is used, megabytesof code have to be copied into RAM, unlike NOR flashes that executein place.The RAM chip is a significant part of the total cost of a phone, bothin dollar terms, and in the cost of the additional power drain required tomaintain its state.It is not only the CPU that places heavy demands on the memory subsystem; all of the bus master peripherals read and write into RAM too.Their demands and contention have to be considered during the systemdesign.

Working out real-world use cases, with bandwidth and latencycalculations, is essential for understanding the requirements placed onthe memory system.2.3.1Mobile SDRAMIn the last few years, memory manufacturers have started to produceRAM specifically for the mobile phone market, known as Low Power orMobile SDRAM.This memory has been optimized for lower power consumption andslower interface speeds of about 100 MHz, compared to normal PCmemory that is four times faster.Mobile memories have additional features to help maintain batterylife.

Power down mode enables the memory controller to disable theRAM part without the need for external control circuitry.Data within a DRAM has to be periodically updated to maintain itsstate. When idle, DRAMs do this using self-refresh circuitry. TemperatureCompensated Self Refresh (TCSR) and Partial Array Self Refresh (PASR)are used to reduce the power consumption when idle. The combinationof TCSR and PASR can reduce the standby current from 150 to 115 µA.2.3.2Internal RAM (IRAM)Memory that is embedded within the SoC is known as internal RAM(IRAM).

There is much less of this than main memory.When booting a system from NAND Flash, core-loader code is copiedfrom the first block of NAND into RAM. IRAM is an ideal target forthis code due to its simple setup. Once the core-loader is running fromIRAM, it will initialize main RAM so that the core OS image can bedecompressed and copied there.IRAM can be used as an internal frame buffer. An LCD controllerdriving a dumb display needs to re-read the entire frame buffer 60 timesa second. Thus a 16-bit QVGA display will require 8.78 MB of data inone second. By moving the frame buffer into IRAM, the system can makea large saving in power and main memory bandwidth.

A dedicated IRAMframe buffer can be further optimized for LCD access and to reduce itspower needs.FLASH MEMORY31IRAM can also be useful as a scratch pad or message box betweenmultiple processors on the SoC.Note that putting small quantities of code into IRAM does not speedup the execution of that code, since the ICache is already doing a betterand faster job.2.4 Flash memorySymbian phones use Flash memory as their principal store of systemcode and user data.

Flash memory is a silicon-based non-volatile storagemedium that can be programmed and erased electronically.The use of Flash memory is bound by its physical operation. Individualbits can only be transformed from the one state into the zero state. Torestore a bit back to a one requires the erasure of a whole block or segmentof Flash, typically 64 KB. Writing a one into a bit position containing azero will leave it unchanged.Flash memory comes in two major types: NOR and NAND.

The namesrefer to their fundamental silicon gate design. Symbian OS phones makebest use of both types of Flash through the selection of file systems – Iwill explain this in detail in Chapter 9, The File Server.The built-in system code and applications appear to Symbian softwareas one large read-only drive, known as the Z: drive. This composite filesystem is made up of execute in place (XIP) code and code that is loadedon demand from the Read Only File System (ROFS).

The Z: drive issometimes known as the ROM image.User data and installed applications reside on the internal, writable C:drive. The C: drive is implemented using one of two different file systems:LFFS (Log Flash File System) for NOR or a standard FAT file system abovea Flash Translation Layer (FTL) on top of NAND.A typical Symbian phone today will use between 32 and 64 MB ofFlash for the code and user data – this is the total ROM budget.Symbian uses many techniques to minimize the code and data sizeswithin a phone, such as THUMB instruction set, prelinked XIP images,compressed executables, compressed data formats and coding standardsthat emphasize minimal code size.2.4.1 NOR FlashNOR Flash is used to store XIP code that is run directly by the CPU.

Itis connected to a static memory bus on the SoC and can be accessed inrandom order just like RAM. The ARM CPU can boot directly out of NORFlash if the Flash is located at physical address zero (0x00000000).For user data, Symbian uses the Log Flash File System (LFFS) on top ofNOR Flash. This file system is optimized to take advantage of NOR Flashcharacteristics. I describe LFFS in detail in Chapter 9, The File Server.32HARDWARE FOR SYMBIAN OSNOR flashes allow for unlimited writes to the same data block, to turnthe ones into zeros. Flashes usually have a write buffer of around 32 to 64bytes that allows a number of bytes to be written in parallel to increasespeed. A buffered write will take between 50 and 600 µs dependingon the bit patterns of the data already in the Flash and the data beingwritten. All zeros or all ones can be fast, and patterns such as 0xA5A5will be slow.Erasing a NOR segment is slow, taking about half a second to onesecond.

But erases can be suspended and later restarted – LFFS uses thisfeature to perform background cleanup of deleted data while remainingresponsive to foreground requests.Completed writes and erases will update the status register within theFlash, and may generate an external interrupt. Without an interrupt, theCPU will need to use a high-speed timer to poll the Flash for completion.By using NOR flashes with Read–While–Write capabilities, it is possible to build a Symbian OS phone with one NOR part containing XIPcode and LFFS data.2.4.2 NAND FlashNAND Flash is treated as a block-based disk, rather than randomlyaddressable memory. Unlike NOR, it does not have any address lines, socannot appear in the memory map.

This means that code cannot executedirectly from NAND and it has to be copied into RAM first. This resultsin the need for extra RAM in a NAND phone compared to a similarNOR device. NAND Flash writes are about 10 times faster than those onNOR Flash.A phone cannot boot directly from NAND. The process is morecomplex, requiring a set of boot loaders that build upon each other,finally resulting in a few megabytes of core Symbian OS image, the ROM,being loaded into RAM, where it will execute.NAND is also inherently less reliable than NOR.

New parts will comewith defective blocks and are susceptible to bit errors during operation.To alleviate the second problem, an Error Correction Code (ECC) iscalculated for every page of data, typically 512 bytes. On every read,the ECC is re-calculated and the difference between it and the storedECC value is used to correct single-bit errors, at runtime.

Multi-bit errorscannot be recovered and the page is considered corrupt.The lower price of NAND compared to NOR makes it attractive formass-market phone projects, even after taking into account the extraRAM required.NAND Flash parts are attached to the SoC using a dedicated interfacethat is connected directly to the NAND chip pins through an 8-bit or 16bit bus.

The interface block will use the DMA interface for data transfers,and contains circuits to calculate the ECC on writes and reads.INTERRUPTS33The NAND interface reads and writes into the NAND Flash usingpages of data. A small block NAND device uses 512-byte pages, and alarge block device uses 2048-byte pages. Data is erased by block, wherea block will contain 32 or 64 pages.2.5 InterruptsPeripherals in the system demand attention from the CPU by generatinginterrupts.

Every peripheral will have one or more interrupt lines attachedto the Programmable Interrupt Controller (PIC), which in turn will funnelthe outstanding interrupts into the CPU. ARM cores only have twointerrupt inputs, the normal Interrupt ReQuest (IRQ) and the Fast InterruptreQuest (FIQ). The FIQ has higher priority than IRQ and an additional setof banked registers.The EKA2 interrupt dispatch code determines the source of an interruptby reading the PIC registers, and then calls the correct service function.This is all explained in Chapter 6, Interrupts and Exceptions.In Figure 2.4, you can see a 62 interrupt system, incorporating a twolayer design that re-uses the same PIC block to cascade from level 2 intolevel 1.CPUIRQFIQPIC Level 1L2 IRQL2 FIQPIC Level 2P1P30Figure 2.4P31Two-layer interrupt controllerP6234HARDWARE FOR SYMBIAN OSEach interrupt within a layer will be represented by one of the 32bits inside the controlling register set.

The registers allow the interruptdispatch software to configure, enable and detect the correct interrupt:Interrupt TypeIRQFIQOutput StatusTrueFalseEnabledTrueFalseLatched Interrupt InputTrueFalseDetect TypeEdgeLevelPolarityRisingEdge/High LevelFallingEdge/Low LevelExamples of interrupt types in use include:A serial port output FIFO will have a half-empty setting, generating a highlevel whenever there is space within the FIFO. Once enough data has beenwritten into the FIFO by an interrupt service routine, the interrupt outputwill drop back.A rising edge interrupt would be used to detect the short VSync pulsegenerated by the LCD controller on the start of a new output frame.To determine the current pending interrupt, the software dispatcher mustread the status and enable registers from the PIC, AND them together,and look for a set bit to determine which interrupt to dispatch.