Wiley.Symbian.OS.Internals.Real.time.Kernel.Programming.Dec.2005.eBook-DDU (779891), страница 11
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The bitnumber is then used to index a table of function pointers to the correctinterrupt service routine (ISR). By putting the highest priority interrupt inthe upper bits of level 1, the first valid bit can be found quickly using thecount leading zeros (CLZ) instruction.The interrupt dispatch latency is the time between the IRQ input beingraised and the execution of the first instruction in the ISR, and is the timetaken up by the software dispatcher described in the previous paragraphand the thread preamble code. It will run for tens of instructions, resultingin about a 50-cycle interrupt cost, or 250 ns on a 200 MHz core. The totaloverhead of an interrupt, once the post-amble code and kernel dispatcheris taken into account, will be approaching 1 µs.You can use more sophisticated PICs to reduce the interrupt latency.Bit patterns are replaced by a status register containing the highest priorityinterrupt number for the dispatch software to use immediately.The ARM vectored interrupt controller (VIC) is an even more complexsystem, in which the CPU has a dedicated VIC port.
It allows for theTIMERS35ISR address to be injected directly into the CPU, removing the overheadof software interrupt dispatch, and saving a few tens of cycles perinterrupt. Symbian OS phones do not require a VIC and its associatedsilicon complexity, as they do not have hard real-time interrupts withnanosecond latencies.When designing a phone you should aim to minimize the numberof active interrupts within the system, as this will increase the overallsystem interrupt response robustness and reduce power consumption.This can be done by using DMA interfaced peripherals, and by notpolling peripherals from fast timers.2.6 TimersIn Chapter 5, Kernel Services, I will explain EKA2’s use of the millisecondtimer. EKA2 uses a 1 ms tick timer to drive time slicing and the timerqueues, and to keep track of wall clock time.The minimum hardware requirement is for a high-speed timer capableof generating regular 1 ms interrupts without drifting. The timer counterneeds to be readable, writable, and the maximum cycle period should bemany seconds.The speed of the timer clock source is not essential to Symbian OS,but somewhere between 32 kHz and 1 MHz is common.
Slower clocksources have lower power consumption, and faster clock rates allowmore flexible use of the timers, beyond the kernel millisecond tick (seeFigure 2.5).The preferred hardware implementation is a free-running 32-bit countercoupled with a set of 32-bit match registers to generate the timer interrupts.They enable simple software schemes for anti-jitter, idle tick suppressionand profiling. Self-reloading countdown timers are an alternative hardware option, but they are less flexible.CLOCKCOUNTERDEBUG_HALTFigure 2.5MATCH 0=MATCH 1=MATCH 2=High-speed timer with three match registers36HARDWARE FOR SYMBIAN OSThe normal operation of the millisecond timer with match registersis straightforward. The external clock source drives the counter, andon every increment the match registers are tested. If they match, theirinterrupt line is raised, the millisecond timer ISR will execute, kernelmillisecond tick processing will occur and then the ISR will re-queue theinterrupt by adding 1 ms worth of clock ticks to the match register.The counter is always allowed to be free-running and the match registeris always incremented from the previous match value.
This produces adrift-free millisecond interrupt. If the input clock frequency is not an exactmultiple of 1 Hz, anti-jitter software will generate an average 1 ms timer,by adding or removing a few extra clock cycles per millisecond interrupt.For the kernel to keep accurate track of time when the CPU is asleep,the timer input clock and the counter circuits must be powered from anindependent source to the core.To debug software running in a system with high-speed timers, it isessential that the JTAG debugger hardware suspends the timers while ithalts the CPU. It does this by the input of a DEBUG_HALT signal intothe timer block. Stopping the timers ensures that the OS is not floodedby timer interrupts during debug single steps, and that the kernel timerqueues are not broken by too much unexpected time elapsing.Multiple timers are required within a real system even though EKA2itself only needs one.
Peripherals with sub-millisecond timing requirements, for example those polling a NOR Flash for write completion,will use an extra timer. Spare timers can also be used for accurateperformance profiling.2.7 Direct Memory Access (DMA)Direct Memory Access (DMA) is used by Symbian OS to offload theburden of high bandwidth memory to peripheral data transfers and allowthe CPU to perform other tasks. DMA can reduce the interrupt load bya factor of 100 for a given peripheral, saving power and increasing thereal-time robustness of that interface.Chapter 13, Peripheral Support, will describe how the EKA2 softwareframework for DMA is used with the different DMA hardware optionsand device drivers.A DMA engine is a bus master peripheral.
It can be programmed tomove large quantities of data between peripherals and memory withoutthe intervention of the CPU.Multi-channel DMA engines are capable of handling more than onetransfer at one time. SoCs for Symbian phones should have as manychannels as peripheral ports that require DMA, and an additional channelfor memory-to-memory copies can be useful.A DMA channel transfer will be initiated by programming the controlregisters with burst configuration commands, transfer size, the physicalLIQUID CRYSTAL DISPLAY (LCD)37addresses of the target RAM and the peripheral FIFO.
This is followedby a DMA start command. The transfers of data will be hardware flowcontrolled by the peripheral interface, since the peripherals will alwaysbe slower than the system RAM.In a memory to peripheral transfer, the DMA engine will wait until theperipheral signals that it is ready for more data. The engine will read aburst of data, typically 8, 16 or 32 bytes, into a DMA internal buffer, andit will then write out the data into the peripheral FIFO. The channel willincrement the read address ready for the next burst until the total transferhas completed, when it will raise a completion interrupt.A DMA engine that raises an interrupt at the end of every transfer issingle-buffered.
The CPU will have to service an interrupt and re-queuethe next DMA transfer before any more data will flow. An audio interfacewill have a real-time response window determined by its FIFO depthand drain rate. The DMA ISR must complete within this time to avoiddata underflow. For example, this time would be about 160 µs for 16-bitstereo audio.Double-buffered DMA engines allow the framework to queue up thenext transfer while the current one is taking place, by having a duplicateset of channel registers that the engine switches between. Doublebuffering increases the real-time response window up to the duration of awhole transfer, for example about 20 ms for a 4 KB audio transfer buffer.Scatter-gather DMA engines add another layer of sophistication andprogrammability. A list of DMA commands is assembled in RAM, andthen the channel is told to process it by loading the first command intothe engine.
At the end of each transfer, the DMA engine will load thenext command – until it runs out of commands. New commands can beadded or updated in the lists while DMA is in progress, so in theory myaudio example need never stop.Scatter-gather engines are good for transferring data into virtual memory systems where the RAM consists of fragmented pages. They are alsogood for complex peripheral interactions where data reads need to beinterspersed with register reads. NAND controllers require 512 bytes ofdata, followed by 16 bytes of metadata and the reading of the ECCregisters for each incoming block.Power savings come from using DMA, since the CPU can be idleduring a transfer, DMA bursts don’t require interrupts or instructions tomove a few bytes of data, and the DMA engine can be tuned to matchthe performance characteristics of the peripheral and memory systems.2.8 Liquid Crystal Display (LCD)The primary display on Symbian OS phones is a color liquid crystaldisplay.
The job of the display is to turn pixels in the frame buffer intoimages we can see.LIQUID CRYSTAL DISPLAY (LCD)37addresses of the target RAM and the peripheral FIFO. This is followedby a DMA start command. The transfers of data will be hardware flowcontrolled by the peripheral interface, since the peripherals will alwaysbe slower than the system RAM.In a memory to peripheral transfer, the DMA engine will wait until theperipheral signals that it is ready for more data. The engine will read aburst of data, typically 8, 16 or 32 bytes, into a DMA internal buffer, andit will then write out the data into the peripheral FIFO. The channel willincrement the read address ready for the next burst until the total transferhas completed, when it will raise a completion interrupt.A DMA engine that raises an interrupt at the end of every transfer issingle-buffered. The CPU will have to service an interrupt and re-queuethe next DMA transfer before any more data will flow.
An audio interfacewill have a real-time response window determined by its FIFO depthand drain rate. The DMA ISR must complete within this time to avoiddata underflow. For example, this time would be about 160 µs for 16-bitstereo audio.Double-buffered DMA engines allow the framework to queue up thenext transfer while the current one is taking place, by having a duplicateset of channel registers that the engine switches between. Doublebuffering increases the real-time response window up to the duration of awhole transfer, for example about 20 ms for a 4 KB audio transfer buffer.Scatter-gather DMA engines add another layer of sophistication andprogrammability.
A list of DMA commands is assembled in RAM, andthen the channel is told to process it by loading the first command intothe engine. At the end of each transfer, the DMA engine will load thenext command – until it runs out of commands. New commands can beadded or updated in the lists while DMA is in progress, so in theory myaudio example need never stop.Scatter-gather engines are good for transferring data into virtual memory systems where the RAM consists of fragmented pages. They are alsogood for complex peripheral interactions where data reads need to beinterspersed with register reads. NAND controllers require 512 bytes ofdata, followed by 16 bytes of metadata and the reading of the ECCregisters for each incoming block.Power savings come from using DMA, since the CPU can be idleduring a transfer, DMA bursts don’t require interrupts or instructions tomove a few bytes of data, and the DMA engine can be tuned to matchthe performance characteristics of the peripheral and memory systems.2.8 Liquid Crystal Display (LCD)The primary display on Symbian OS phones is a color liquid crystaldisplay.
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