Wiley.Symbian.OS.Internals.Real.time.Kernel.Programming.Dec.2005.eBook-DDU (779891), страница 9
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This lookup has to happen on every memory access.The MMU breaks up the flat contiguous physical memory into pages.Mostly they are small, 4 KB pages, although larger 64 KB pages and 1 MBsections exist.The Symbian OS virtual memory map re-orders scattered physicalpages into an apparently ordered virtual memory space.
The re-orderinginformation is expressed to the MMU through the use of page tables.Page tables are a hierarchical data structure that encode the entire 4 GBvirtual address space in a sparse manner. On ARM systems the table hastwo levels, the Page Directory and Page Tables.In much the same way as a physical address is decoded by the buscontrollers, the bit fields within a virtual address are decoded by theMMU into the Page Directory, the Page Table and index into the memorypage. This is explained in detail in Section 7.2.1.Bits31 → 2019 → 1211 → 0AddressdecodeTop 12 bitsmap to PageDirectoryMiddle 8 bitsmap to PageTableBottom 12bits are offsetin pageVirtual address decoding for a small pageOn every memory access the MMU performs a virtual to physical lookupto get the correct bus address and to validate page permissions.
Theprocess of looking up a physical address from a virtual one is known as‘‘walking’’ the page tables. This takes the time required for two memoryaccesses, the read of the Page Directory followed by the Page Table read.To speed up the address translation the MMU caches recently lookedup results within a Translation Look-aside Buffer (TLB). If a virtual tophysical lookup cannot be found in a TLB, the MMU has table walking26HARDWARE FOR SYMBIAN OShardware to perform a new virtual lookup and it will save the result intoa TLB entry.The TLBs must be flushed if the page tables are changed. This canhappen on a context switch, during debug or the unloading of code.At startup the CPU will run using physical addresses and the bootstrapcode will build the initial set of page tables.
When the MMU is turned onthe CPU will switch into virtual memory operation, ready for the kernelboot sequence.2.2.5 CachesThe CPUs used in every Symbian phone require caches to achieveoptimum performance. The job of a cache is to insulate the fast CPU fromits slower memory system by holding local copies of recently accesseddata or instructions.ARM CPUs have Harvard architectures, with separate instruction anddata ports, resulting in separate instruction and data caches (ICache,DCache).Caches work by taking advantage of the repetitive local characteristicsof executing code.
Code that is in a loop will execute the same instructionsand access the same or similar data structures. As long as the CPU’s viewinto memory is consistent, it does not care where the data is located at anyinstant in time – whether it is found in RAM or in the cache. However,the kernel does not cache memory mapped peripherals because thecontrolling software requires strict ordering of reads and writes into theperipheral registers.Caches are organized in cache lines, which typically contain 32 bytesof data from a 32-byte aligned address, and a tag to store this sourceaddress.
A 16 KB cache would contain 512 lines.When the CPU requests data, the cache tests to see if it has a linethat matches the requested address. If it does, the data is returnedimmediately – this is called a cache hit. If the cache does not contain thedata, then a cache miss has occurred. After a miss, there will be a cacheline fill of the required data from the memory system, and then the CPUwill continue execution. To make space for this new cache line, an oldercache line will be evicted from the cache.The efficiency of a cache is measured by its hit ratio – the ratio ofcache hits to total accesses.
On Symbian OS, the approximate numbersare 95% for the ICache and 90% for the DCache.With a high hit rate, the CPU can run close to its maximum speedwithout being stalled by the memory system. This is good for performanceand even better for battery life, since a cache hit requires substantiallyless power than an external memory access.Line fill operations are optimized for the memory system, to takeadvantage of sequential burst modes from the memory chips.SYSTEM-ON-CHIP (SoC)27Once the MMU has been set up and the cache enabled, all of itsoperation is automatic and the system runs faster.
EKA2 only needs toissue cache control commands if the caches need to be flushed. This canbe due to any of the following:• A memory map change on a context switch• New code being loaded or existing code discarded• Self-modifying code generation• Using DMA from cached memory.2.2.5.1 Virtual and physical cachesThe CPU is isolated from the system bus by the MMU and caches, sotheir order of operation has an impact on Symbian OS (see Figure 2.3).When the CPU is connected directly to the cache, the cache usesvirtual addresses, and it in turn talks through the MMU to generatephysical addresses on the system bus (left-hand side of Figure 2.3).A physically addressed cache will be connected directly to the systembus and will be indexed with real physical addresses.
The virtual tophysical lookup will occur in the MMU, which is located between theCPU and the cache (right-hand side of Figure 2.3).Virtual CachesPhysical CachesCPUCPUCachesVirtual addressPhysical addressVirtual addressPhysical addressMMUMMUCachesSystem BusSystem BusFigure 2.3Virtual and physical caches2.2.5.2 ARM v5 virtual cacheIn ARM v5 and earlier systems, the MMU was placed outside the CPUand caches, resulting in caches that worked within the virtual memorydomain of the MMU.In this design, all data stored in the cache is indexed by its virtualaddress, so when the CPU requests data with a virtual address, no MMUtranslation is required for a cache hit.
If there is a miss, the MMU is28HARDWARE FOR SYMBIAN OSinvoked to generate a physical bus address for the cache miss. Thisdesign reduces the workload on the MMU and saves power.The downside to virtual caches is that the kernel has to empty themevery time it modifies the page tables. The kernel can invalidate theICache (discard it) but it has to flush all of the dirty data in the DCache tothe memory system.Unfortunately, the Symbian OS moving memory model modifies thevirtual address map when it performs inter-process context switch.
Thismeans that a cache flush is needed that can take many milliseconds,resulting in a significant loss of system performance. In Section 7.2.1,you will see that Symbian OS uses a technique called fixed processes tominimize these cache flushes.2.2.5.3 ARM v6 physical cacheARM architecture v6 delivered a whole new MMU, with new page tablelayout, physical caches, process ASIDs, support for level 2 caches and IOmemory space.An ARM v6 CPU, such as the 1136, uses physical addresses at alltimes in the cache.
This requires the MMU to work harder by performinga virtual to physical lookup on every request from the CPU core. This willnormally be through a TLB lookup.The advantage to this scheme is that the caches are always in syncwith the physical memory map, no matter how the virtual map changes.This removes the cache flush penalty from context switches.To further improve performance, the v6 MMU model introducedApplication Space Identifiers, known as ASIDs. Each ASID has its own 4or 8 KB PDE, for the bottom 1 or 2 GB of address space.
Changing theASID will instantly swap out this address space.As I will explain in Section 7.4.2, EKA2 assigns an ASID to everyprocess it creates, resulting in extremely fast context switches.2.2.5.4 Instruction cache (ICache)The ICache contains recently executed instructions, ready for their re-use.Instructions cannot be modified in the ICache, so it can be treated as aread-only device.When a line needs to be evicted on a cache miss, it is immediatelyoverwritten by the new instructions. This is permitted, since it is read-onlyand cannot have changed. Cache flushing operations are only neededwhen code is unloaded from the system and to ensure the coherency ofgenerated or self-modifying code.Code compiled for the THUMB instruction set gains an advantage overARM by being able to fit twice as many instructions into the ICache. Thishelps to offset its slower performance.RANDOM ACCESS MEMORY (RAM)292.2.5.5 Data cache (DCache)When the CPU is reading data, the DCache works in the same way asthe ICache.
Data hits within the cache are returned immediately andmissed data will be sourced from main memory, replacing a recentlyevicted line.The complexity comes with data writes into the DCache and thecombinations of strategies to return it to memory.With write-through caching, every time the CPU writes data, it willbe immediately written out to memory, through the write buffer, and thedata will update the cached copy if it hits.Write-through caching ensures that memory always stays coherentwith the cache. Cache line evictions and cache cleaning operations donot need to write anything back to memory, enabling them to discardlines at will.The downside is that the system bus has to support the full write speedof the CPU and the cache is only being effective for reads.Symbian OS uses write-through caching for the LCD frame buffer, toensure consistent pixels on the display.
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