ATmega128 (961843), страница 62
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It canalso be used as an idle state between JTAG sequences. The state machine sequencefor changing the instruction word is shown in Figure 146.308ATmega1282467M–AVR–11/04ATmega128Figure 146. State Machine Sequence for Changing the Instruction Word1Test-Logic-Reset00Run-Test/Idle1Select-DR Scan1Select-IR Scan0011Capture-DRCapture-IR000Shift-DR11Exit1-DR00Pause-DR0Pause-IR110Exit2-DRExit2-IR11Update-DRAVR_RESET ($C)1Exit1-IR010Shift-IR101Update-IR010The AVR specific public JTAG instruction for setting the AVR device in the Reset modeor taking the device out from the Reset mode. The TAP controller is not reset by thisinstruction.
The one bit Reset Register is selected as Data Register. Note that the resetwill be active as long as there is a logic 'one' in the Reset Chain. The output from thischain is not latched.The active states are:•PROG_ENABLE ($4)Shift-DR: The Reset Register is shifted by the TCK input.The AVR specific public JTAG instruction for enabling programming via the JTAG port.The 16-bit Programming Enable Register is selected as data register. The active statesare the following:•Shift-DR: the programming enable signature is shifted into the data register.•Update-DR: the programming enable signature is compared to the correct value,and Programming mode is entered if the signature is valid.3092467M–AVR–11/04PROG_COMMANDS ($5)PROG_PAGELOAD ($6)The AVR specific public JTAG instruction for entering programming commands via theJTAG port.
The 15-bit Programming Command Register is selected as data register.The active states are the following:•Capture-DR: the result of the previous command is loaded into the data register.•Shift-DR: the data register is shifted by the TCK input, shifting out the result of theprevious command and shifting in the new command.•Update-DR: the programming command is applied to the Flash inputs.•Run-Test/Idle: one clock cycle is generated, executing the applied command.The AVR specific public JTAG instruction to directly load the Flash data page via theJTAG port.
The 2048-bit Virtual Flash Page Load Register is selected as data register.This is a virtual scan chain with length equal to the number of bits in one Flash page.Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR stateis not used to transfer data from the Shift Register. The data are automatically transferred to the Flash page buffer byte by byte in the Shift-DR state by an internal statemachine. This is the only active state:•Shift-DR: Flash page data are shifted in from TDI by the TCK input, andautomatically loaded into the Flash page one byte at a time.Note:PROG_PAGEREAD ($7)The AVR specific public JTAG instruction to read one full Flash data page via the JTAGport.
The 2056-bit Virtual Flash Page Read Register is selected as data register. This isa virtual scan chain with length equal to the number of bits in one Flash page plus 8.Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DRstate is not used to transfer data to the Shift Register. The data are automatically transferred from the Flash page buffer byte by byte in the Shift-DR state by an internal statemachine.
This is the only active state:•Shift-DR: Flash data are automatically read one byte at a time and shifted out onTDO by the TCK input. The TDI input is ignored.Note:Data Registers310The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the firstdevice in JTAG scan chain. If the AVR cannot be the first device in the scan chain, thebyte-wise programming algorithm must be used.The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the firstdevice in JTAG scan chain. If the AVR cannot be the first device in the scan chain, thebyte-wise programming algorithm must be used.The data registers are selected by the JTAG instruction registers described in section“Programming Specific JTAG Instructions” on page 308. The data registers relevant forprogramming operations are:•Reset Register•Programming Enable Register•Programming Command Register•Virtual Flash Page Load Register•Virtual Flash Page Read RegisterATmega1282467M–AVR–11/04ATmega128Reset RegisterThe Reset Register is a Test Data Register used to reset the part during programming.
Itis required to reset the part before entering programming mode.A high value in the Reset Register corresponds to pulling the external Reset low. Thepart is reset as long as there is a high value present in the Reset Register. Dependingon the Fuse settings for the clock options, the part will remain reset for a Reset TimeOut Period (refer to “Clock Sources” on page 35) after releasing the Reset Register. Theoutput from this Data Register is not latched, so the reset will take place immediately, asshown in Figure 123 on page 256.Programming Enable RegisterThe Programming Enable Register is a 16-bit register. The contents of this register iscompared to the programming enable signature, binary code 1010_0011_0111_0000.When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The Register is reset to 0 on Power-on Reset,and should always be reset when leaving Programming mode.Figure 147.
Programming Enable RegisterTDIDATA$A370=DQProgramming enableClockDR & PROG_ENABLETDO3112467M–AVR–11/04Programming CommandRegisterThe Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previouscommand, if any. The JTAG Programming Instruction Set is shown in Table 130. Thestate sequence when shifting in the programming commands is illustrated in Figure 149.Figure 148. Programming Command RegisterTDISTROBESADDRESS/DATAFlashEEPROMFusesLock BitsTDO312ATmega1282467M–AVR–11/04ATmega128Table 130.
JTAG Programming InstructionSet a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t careInstructionTDI sequenceTDO sequenceNotes1a. Chip erase0100011_100000000110001_100000000110011_100000000110011_10000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx1b. Poll for chip erase complete0110011_10000000xxxxxox_xxxxxxxx2a. Enter Flash Write0100011_00010000xxxxxxx_xxxxxxxx2b. Load Address High Byte0000111_aaaaaaaaxxxxxxx_xxxxxxxx2c. Load Address Low Byte0000011_bbbbbbbbxxxxxxx_xxxxxxxx2d. Load Data Low Byte0010011_iiiiiiiixxxxxxx_xxxxxxxx2e. Load Data High Byte0010111_iiiiiiiixxxxxxx_xxxxxxxx2f.
Latch Data0110111_000000001110111_000000000110111_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx(1)2g. Write Flash Page0110111_000000000110101_000000000110111_000000000110111_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx(1)2h. Poll for Page Write complete0110111_00000000xxxxxox_xxxxxxxx(2)3a.
Enter Flash Read0100011_00000010xxxxxxx_xxxxxxxx3b. Load Address High Byte0000111_aaaaaaaaxxxxxxx_xxxxxxxx3c. Load Address Low Byte0000011_bbbbbbbbxxxxxxx_xxxxxxxx3d. Read Data Low and High Byte0110010_000000000110110_000000000110111_00000000xxxxxxx_xxxxxxxxxxxxxxx_ooooooooxxxxxxx_oooooooo4a.
Enter EEPROM Write0100011_00010001xxxxxxx_xxxxxxxx4b. Load Address High Byte0000111_aaaaaaaaxxxxxxx_xxxxxxxx4c. Load Address Low Byte0000011_bbbbbbbbxxxxxxx_xxxxxxxx4d. Load Data Byte0010011_iiiiiiiixxxxxxx_xxxxxxxx4e. Latch Data0110111_000000001110111_000000000110111_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx(1)4f. Write EEPROM Page0110011_000000000110001_000000000110011_000000000110011_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx(1)4g. Poll for Page Write complete0110011_00000000xxxxxox_xxxxxxxx(2)5a. Enter EEPROM Read0100011_00000011xxxxxxx_xxxxxxxx5b.
Load Address High Byte0000111_aaaaaaaaxxxxxxx_xxxxxxxx(2)(9)(9)low bytehigh byte(9)(9)3132467M–AVR–11/04Table 130. JTAG Programming Instruction (Continued)Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t careInstructionTDI sequenceTDO sequence5c. Load Address Low Byte0000011_bbbbbbbbxxxxxxx_xxxxxxxx5d. Read Data Byte0110011_bbbbbbbb0110010_000000000110011_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_oooooooo0100011_01000000xxxxxxx_xxxxxxxx6b. Load Data Low Byte0010011_iiiiiiiixxxxxxx_xxxxxxxx(3)6c. Write Fuse Extended byte0111011_000000000111001_000000000111011_000000000111011_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx(1)6d.
Poll for Fuse Write complete0110111_00000000xxxxxox_xxxxxxxx(2)6e. Load Data Low Byte(7)0010011_iiiiiiiixxxxxxx_xxxxxxxx(3)6f. Write Fuse High byte0110111_000000000110101_000000000110111_000000000110111_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx(1)6g. Poll for Fuse Write complete0110111_00000000xxxxxox_xxxxxxxx(2)6h. Load Data Low Byte0010011_iiiiiiiixxxxxxx_xxxxxxxx(3)6i. Write Fuse Low byte0110011_000000000110001_000000000110011_000000000110011_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx(1)6j.
Poll for Fuse Write complete0110011_00000000xxxxxox_xxxxxxxx(2)7a. Enter Lock bit Write0100011_00100000xxxxxxx_xxxxxxxx7b. Load Data Byte0010011_11iiiiiixxxxxxx_xxxxxxxx(4)7c. Write Lock bits0110011_000000000110001_000000000110011_000000000110011_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx(1)7d. Poll for Lock bit Write complete0110011_00000000xxxxxox_xxxxxxxx(2)8a. Enter Fuse/Lock bit Read0100011_00000100xxxxxxx_xxxxxxxx8b. Read Extended Fuse Byte(6)0111010_000000000111011_00000000xxxxxxx_xxxxxxxxxxxxxxx_oooooooo8c. Read Fuse High Byte(7)0111110_000000000111111_00000000xxxxxxx_xxxxxxxxxxxxxxx_oooooooo8d. Read Fuse Low Byte(8)0110010_000000000110011_00000000xxxxxxx_xxxxxxxxxxxxxxx_oooooooo8e.
Read Lock bits(9)0110110_000000000110111_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxoooooo6a. Enter Fuse Write(6)(7)(9)314Notes(5)ATmega1282467M–AVR–11/04ATmega128Table 130. JTAG Programming Instruction (Continued)Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t careInstructionTDI sequenceTDO sequenceNotes8f.
Read Fuses and Lock bits0111010_000000000111110_000000000110010_000000000110110_000000000110111_00000000xxxxxxx_xxxxxxxxxxxxxxx_ooooooooxxxxxxx_ooooooooxxxxxxx_ooooooooxxxxxxx_oooooooo(5)fuse ext. bytefuse high bytefuse low bytelock bits9a. Enter Signature Byte Read0100011_00001000xxxxxxx_xxxxxxxx9b. Load Address Byte0000011_bbbbbbbbxxxxxxx_xxxxxxxx9c. Read Signature Byte0110010_000000000110011_00000000xxxxxxx_xxxxxxxxxxxxxxx_oooooooo10a.
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