ATmega128 (961732), страница 7
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The External Memory Interface is designed in compliance tothe 74AHC series latch. However, most latches can be used as long they comply withthe main timing parameters. The main parameters for the address latch are:•D to Q propagation delay (tPD).•Data setup time before G low (tSU).•Data (address) hold time after G low (TH).The External Memory Interface is designed to guaranty minimum address hold timeafter G is asserted low of th = 5 ns. Refer to tLAXX_LD/tLLAXX_ST in “External Data MemoryTiming” Tables 137 through Tables 144 on pages 330 - 332. The D-to-Q propagationdelay (tPD) must be taken into consideration when calculating the access time requirement of the external component.
The data setup time before G low (t SU ) must notexceed address valid to ALE low (tAVLLC) minus PCB wiring delay (dependent on thecapacitive load).Figure 12. External SRAM Connected to the AVRD[7:0]AD7:0DALEGAVRA15:8RDWR26QA[7:0]SRAMA[15:8]RDWRATmega1282467M–AVR–11/04ATmega128Pull-up and Bus-keeperThe pull-ups on the AD7:0 ports may be activated if the corresponding Port register iswritten to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep.The XMEM interface also provides a bus-keeper on the AD7:0 lines.
The bus-keepercan be disabled and enabled in software as described in “External Memory Control Register B – XMCRB” on page 31. When enabled, the bus-keeper will ensure a defined logiclevel (zero or one) on the AD7:0 bus when these lines would otherwise be tri-stated bythe XMEM interface.TimingExternal Memory devices have different timing requirements. To meet these requirements, the ATmega128 XMEM interface provides four different wait-states as shown inTable 4.
It is important to consider the timing specification of the External Memorydevice before selecting the wait-state. The most important parameters are the accesstime for the external memory compared to the set-up requirement of the ATmega128.The access time for the External Memory is defined to be the time from receiving thechip select/address until the data of this address actually is driven on the bus. Theaccess time cannot exceed the time from the ALE pulse must be asserted low until datais stable during a read sequence (See tLLRL+ tRLRH - tDVRH in Tables 137 through Tables144 on pages 330 - 332).
The different wait-states are set up in software. As an additional feature, it is possible to divide the external memory space in two sectors withindividual wait-state settings. This makes it possible to connect two different memorydevices with different timing requirements to the same XMEM interface. For XMEMinterface timing details, please refer to Table 137 to Table 144 and Figure 156 to Figure159 in the “External Data Memory Timing” on page 330.Note that the XMEM interface is asynchronous and that the waveforms in the followingfigures are related to the internal system clock. The skew between the internal andexternal clock (XTAL1) is not guarantied (varies between devices temperature, and supply voltage).
Consequently, the XMEM interface is not suited for synchronous operation.Figure 13. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)T1T2T3T4System Clock (CLKCPU )ALEA15:8Prev. addr.DA7:0Prev. dataAddressDA7:0 (XMBK = 0)Prev. dataAddressDA7:0 (XMBK = 1)Prev. dataAddressXXWriteAddressDataWRXXXXXDataXXXXXXXXReadDataRDNote:1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (uppersector) or SRW00 (lower sector).
The ALE pulse in period T4 is only present if thenext instruction accesses the RAM (internal or external).272467M–AVR–11/04Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)T1T2T3T4T5System Clock (CLKCPU )ALEA15:8Prev. addr.DA7:0Prev. dataAddressDA7:0 (XMBK = 0)Prev. dataAddressDA7:0 (XMBK = 1)Prev.
dataXXWriteAddressDataWRAddressReadDataDataRDNote:1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (uppersector) or SRW00 (lower sector).The ALE pulse in period T5 is only present if the next instruction accesses the RAM(internal or external).Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1)T1T2T3T4T5T6System Clock (CLKCPU )ALEA15:8Prev. addr.DA7:0Prev. dataAddressDA7:0 (XMBK = 0)Prev.
dataAddressDA7:0 (XMBK = 1)Prev. dataXXDataWriteAddressWRDataReadAddressDataRDNote:281. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (uppersector) or SRW00 (lower sector).The ALE pulse in period T6 is only present if the next instruction accesses the RAM(internal or external).ATmega1282467M–AVR–11/04ATmega128Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)T1T2T3T4T5T6T7System Clock (CLKCPU )ALEA15:8Prev.
addr.DA7:0Prev. dataAddressDA7:0 (XMBK = 0)Prev. dataAddressDA7:0 (XMBK = 1)Prev. dataXXWriteAddressDataWRAddressReadDataDataRDNote:1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (uppersector) or SRW00 (lower sector).The ALE pulse in period T7 is only present if the next instruction accesses the RAM(internal or external).XMEM Register DescriptionMCU Control Register –MCUCRBit76543210SRESRW10SESM1SM0SM2IVSELIVCERead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000MCUCR• Bit 7 – SRE: External SRAM/XMEM EnableWriting SRE to one enables the External Memory Interface.The pin functions AD7:0,A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers.
Writing SRE tozero, disables the External Memory Interface and the normal pin and data direction settings are used.• Bit 6 – SRW10: Wait-state Select BitFor a detailed description in non-ATmega103 compatibility mode, see common description for the SRWn bits below (XMCRA description). In ATmega103 compatibility mode,writing SRW10 to one enables the wait-state and one extra cycle is added duringread/write strobe as shown in Figure 14.External Memory ControlRegister A – XMCRABit76543210–SRL2SRL1SRL0SRW01SRW00SRW11–Read/WriteRR/WR/WR/WR/WR/WR/WRInitial Value00000000XMCRA• Bit 7 – Res: Reserved BitThis is a reserved bit and will always read as zero.
When writing to this address location,write this bit to zero for compatibility with future devices.• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit292467M–AVR–11/04It is possible to configure different wait-states for different External Memory addresses.The external memory address space can be divided in two sectors that have separatewait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table3 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and theentire external memory address space is treated as one sector.
When the entire SRAMaddress space is configured as one sector, the wait-states are configured by theSRW11 and SRW10 bits.Table 3. Sector limits with different settings of SRL2..0SRL2SRL1SRL0Sector Limits000Lower sector = N/AUpper sector = 0x1100 - 0xFFFF001Lower sector = 0x1100 - 0x1FFFUpper sector = 0x2000 - 0xFFFF010Lower sector = 0x1100 - 0x3FFFUpper sector = 0x4000 - 0xFFFF011Lower sector = 0x1100 - 0x5FFFUpper sector = 0x6000 - 0xFFFF100Lower sector = 0x1100 - 0x7FFFUpper sector = 0x8000 - 0xFFFF101Lower sector = 0x1100 - 0x9FFFUpper sector = 0xA000 - 0xFFFF110Lower sector = 0x1100 - 0xBFFFUpper sector = 0xC000 - 0xFFFF111Lower sector = 0x1100 - 0xDFFFUpper sector = 0xE000 - 0xFFFF• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait-state Select Bits for UpperSectorThe SRW11 and SRW10 bits control the number of wait-states for the upper sector ofthe external memory address space, see Table 4.• Bit 3..2 – SRW01, SRW00: Wait-state Select Bits for Lower SectorThe SRW01 and SRW00 bits control the number of wait-states for the lower sector ofthe external memory address space, see Table 4.Table 4.
Wait States(1)SRWn1SRWn000No wait-states01Wait one cycle during read/write strobe10Wait two cycles during read/write strobe11Note:Wait StatesWait two cycles during read/write and wait one cycle before driving outnew address1. n = 0 or 1 (lower/upper sector).For further details of the timing and wait-states of the External Memory Interface, seeFigures 13 through Figures 16 for how the setting of the SRW bits affects the timing.• Bit 0 – Res: Reserved BitThis is a reserved bit and will always read as zero.
When writing to this address location,write this bit to zero for compatibility with future devices.30ATmega1282467M–AVR–11/04ATmega128External Memory ControlRegister B – XMCRBBit76543210XMBK––––XMM2XMM1XMM0Read/WriteR/WRRRRR/WR/WR/WInitial Value00000000XMCRB• Bit 7– XMBK: External Memory Bus-keeper EnableWriting XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeperis enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they wouldotherwise be tri-stated.
Writing XMBK to zero disables the bus keeper. XMBK is notqualified with SRE, so even if the XMEM interface is disabled, the bus keepers are stillactivated as long as XMBK is one.• Bit 6..4 – Res: Reserved BitsThese are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High MaskWhen the External Memory is enabled, all Port C pins are default used for the highaddress byte.
If the full 60KB address space is not required to access the External Memory, some, or all, Port C pins can be released for normal Port Pin function as describedin Table 5. As described in “Using all 64KB Locations of External Memory” on page 33,it is possible to use the XMMn bits to access all 64KB locations of the External Memory.Table 5. Port C Pins Released as Normal Port Pins when the External Memory isEnabledUsing all Locations ofExternal Memory Smaller than64 KBXMM2XMM1XMM0# Bits for External Memory AddressReleased Port Pins0008 (Full 60 KB space)None0017PC70106PC7 - PC60115PC7 - PC51004PC7 - PC41013PC7 - PC31102PC7 - PC2111No Address high bitsFull Port CSince the external memory is mapped after the internal memory as shown in Figure 11,the external memory is not addressed when addressing the first 4,352 bytes of dataspace.
It may appear that the first 4,352 bytes of the external memory are inaccessible(external memory addresses 0x0000 to 0x10FF). However, when connecting an external memory smaller than 64 KB, for example 32 KB, these locations are easily accessedsimply by addressing from address 0x8000 to 0x90FF. Since the External MemoryAddress bit A15 is not connected to the external memory, addresses 0x8000 to 0x90FFwill appear as addresses 0x0000 to 0x10FF for the external memory. Addressing aboveaddress 0x90FF is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To the Application software,the external 32 KB memory will appear as one linear 32 KB address space from 0x1100to 0x90FF.
This is illustrated in Figure 17. Memory configuration B refers to theATmega103 compatibility mode, configuration A to the non-compatible mode.312467M–AVR–11/04When the device is set in ATmega103 compatibility mode, the internal address space is4,096 bytes. This implies that the first 4,096 bytes of the external memory can beaccessed at addresses 0x8000 to 0x8FFF. To the Application software, the external 32KB memory will appear as one linear 32 KB address space from 0x1000 to 0x8FFF.Figure 17. Address Map with 32 KB External MemoryMemory Configuration BMemory Configuration AAVR Memory Map0x0000External 32K SRAMAVR Memory Map0x0000Internal Memory0x10FF0x11000x7FFF0x80000x10FF0x1100ExternalMemory0x90FF0x91000x7FFF0x00000x0FFF0x10000x7FFF0x8000320x0000Internal MemoryExternal0x0FFF0x10000x7FFFMemory0x8FFF0x9000(Unused)0xFFFFExternal 32K SRAM(Unused)0xFFFFATmega1282467M–AVR–11/04ATmega128Using all 64KB Locations ofExternal MemorySince the External Memory is mapped after the Internal Memory as shown in Figure 11,only 60KB of External Memory is available by default (address space 0x0000 to 0x10FFis reserved for internal memory).
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