ATmega128 (961732), страница 5
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This SRAM willoccupy an area in the remaining address locations in the 64K address space. This areastarts at the address following the internal SRAM. The Register file, I/O, Extended I/Oand Internal SRAM occupies the lowest 4352 bytes in normal mode, and the lowest4096 bytes in the ATmega103 compatibility mode (Extended I/O not present), so whenusing 64KB (65536 bytes) of External Memory, 61184 Bytes of External Memory areavailable in normal mode, and 61440 Bytes in ATmega103 compatibility mode. See“External Memory Interface” on page 24 for details on how to take advantage of theexternal memory map.When the addresses accessing the SRAM memory space exceeds the internal datamemory locations, the external data SRAM is accessed using the same instructions asfor the internal data memory access.
When the internal data memories are accessed,the read and write strobe pins (PG0 and PG1) are inactive during the whole accesscycle. External SRAM operation is enabled by setting the SRE bit in the MCUCRRegister.Accessing external SRAM takes one additional clock cycle per byte compared to accessof the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,PUSH, and POP take one additional clock cycle.
If the Stack is placed in externalSRAM, interrupts, subroutine calls and returns take three clock cycles extra because thetwo-byte program counter is pushed and popped, and external memory access does nottake advantage of the internal pipe-line memory access. When external SRAM interfaceis used with wait-state, one-byte external access takes two, three, or four additionalclock cycles for one, two, and three wait-states respectively. Interrupts, subroutine callsand returns will need five, seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states.172467M–AVR–11/04The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
Inthe Register file, registers R26 to R31 feature the indirect addressing pointer registers.The direct addressing reaches the entire data space.The Indirect with Displacement mode reaches 63 address locations from the baseaddress given by the Y- or Z-register.When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.The 32 general purpose working registers, 64 I/O registers, and the 4096 bytes of internal data SRAM in the ATmega128 are all accessible through all these addressingmodes. The Register file is described in “General Purpose Register File” on page 10.Figure 9.
Data Memory MapMemory Configuration AData Memory32 Registers64 I/O Registers160 Ext I/O Reg.Memory Configuration BData Memory$0000 - $001F$0020 - $005F$0060 - $00FF$0100Internal SRAM(4096 x 8)32 Registers64 I/O RegistersInternal SRAM(4000 x 8)$0FFF$1000$10FF$1100External SRAM(0 - 64K x 8)External SRAM(0 - 64K x 8)$FFFF18$0000 - $001F$0020 - $005F$0060$FFFFATmega1282467M–AVR–11/04ATmega128Data Memory Access TimesThis section describes the general access timing concepts for internal memory access.The internal data SRAM access is performed in two clkCPU cycles as described in Figure10.Figure 10. On-chip Data SRAM Access CyclesT1T2T3clkCPUAddressAddress validCompute AddressWriteDataWRReadDataRDMemory access instructionEEPROM Data MemoryNext instructionThe ATmega128 contains 4K bytes of data EEPROM memory.
It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has anendurance of at least 100,000 write/erase cycles. The access between the EEPROMand the CPU is described in the following, specifying the EEPROM Address Registers,the EEPROM Data Register, and the EEPROM Control Register.“Memory Programming” on page 288 contains a detailed description on EEPROM programming in SPI, JTAG, or Parallel Programming modeEEPROM Read/Write AccessThe EEPROM access registers are accessible in the I/O space.The write access time for the EEPROM is given in Table 2.
A self-timing function, however, lets the user software detect when the next byte can be written. If the user codecontains instructions that write the EEPROM, some precautions must be taken. Inheavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. Thiscauses the device for some period of time to run at a voltage lower than specified asminimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page23. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.When the EEPROM is read, the CPU is halted for four clock cycles before the nextinstruction is executed. When the EEPROM is written, the CPU is halted for two clockcycles before the next instruction is executed.EEPROM Address Register –EEARH and EEARLBitRead/WriteInitial Value15141312111098––––EEAR11EEAR10EEAR9EEAR8EEARHEEAR7EEAR6EEAR5EEAR4EEAR3EEAR2EEAR1EEAR0EEARL76543210RRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W0000XXXXXXXXXXXX• Bits 15..12 – Res: Reserved Bits192467M–AVR–11/04These are reserved bits and will always read as zero.
When writing to this address location, write these bits to zero for compatibility with future devices.• Bits 11..0 – EEAR11..0: EEPROM AddressThe EEPROM Address Registers – EEARH and EEARL – specify the EEPROMaddress in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value mustbe written before the EEPROM may be accessed.EEPROM Data Register –EEDRBit7654321MSB0LSBRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000EEDR• Bits 7..0 – EEDR7.0: EEPROM DataFor the EEPROM write operation, the EEDR Register contains the data to be written tothe EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given byEEAR.EEPROM Control Register –EECRBit76543210––––EERIEEEMWEEEWEEERERead/WriteRRRRR/WR/WR/WR/WInitial Value000000X0EECR• Bits 7..4 – Res: Reserved BitsThese bits are reserved bits in the ATmega128 and will always read as zero.• Bit 3 – EERIE: EEPROM Ready Interrupt EnableWriting EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set.Writing EERIE to zero disables the interrupt.
The EEPROM Ready interrupt generates aconstant interrupt when EEWE is cleared.• Bit 2 – EEMWE: EEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to bewritten. When EEMWE is written to one, writing EEWE to one within four clock cycleswill write data to the EEPROM at the selected address.
If EEMWE is zero, writing EEWEto one will have no effect. When EEMWE has been written to one by software, hardwareclears the bit to zero after four clock cycles. See the description of the EEWE bit for anEEPROM write procedure.• Bit 1 – EEWE: EEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. Whenaddress and data are correctly set up, the EEWE bit must be set to write the value intothe EEPROM. The EEMWE bit must be set when the logical one is written to EEWE,otherwise no EEPROM write takes place. The following procedure should be followedwhen writing the EEPROM (the order of steps 3 and 4 is not essential):1.
Wait until EEWE becomes zero.2. Wait until SPMEN in SPMCSR becomes zero.3. Write new EEPROM address to EEAR (optional).4. Write new EEPROM data to EEDR (optional).20ATmega1282467M–AVR–11/04ATmega1285. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.The EEPROM can not be programmed during a CPU write to the Flash memory.
Thesoftware must check that the Flash programming is completed before initiating a newEEPROM write. Step 2 is only relevant if the software contains a boot loader allowingthe CPU to program the Flash. If the Flash is never being updated by the CPU, step 2can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” onpage 275 for details about boot programming.Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since theEEPROM Master Write Enable will time-out. If an interrupt routine accessing theEEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will bemodified, causing the interrupted EEPROM access to fail.
It is recommended to havethe global interrupt flag cleared during the four last steps to avoid these problems.When the write access time has elapsed, the EEWE bit is cleared by hardware. Theuser software can poll this bit and wait for a zero before writing the next byte. WhenEEWE has been set, the CPU is halted for two cycles before the next instruction isexecuted.• Bit 0 – EERE: EEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When thecorrect address is set up in the EEAR Register, the EERE bit must be written to a logicone to trigger the EEPROM read. The EEPROM read access takes one instruction, andthe requested data is available immediately.
When the EEPROM is read, the CPU ishalted for four cycles before the next instruction is executed.The user should poll the EEWE bit before starting the read operation. If a write operationis in progress, it is neither possible to read the EEPROM, nor to change the EEARRegister.The calibrated Oscillator is used to time the EEPROM accesses. Table 2 lists the typicalprogramming time for EEPROM access from the CPU.Table 2.
EEPROM Programming TimeSymbolNumber of Calibrated RCOscillator Cycles(1)Typ Programming TimeEEPROM Write (from CPU)84488.5 msNote:1. Uses 1 MHz clock, independent of CKSEL-fuse settings.212467M–AVR–11/04The following code examples show one assembly and one C function for writing to theEEPROM.
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