Peter I. Corke - Pumaservo - The Unimation Puma servo system.rar (779752), страница 3
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This bus has one line per servo card. Each board asserts its line (activehigh) when the in-tolerance condition is true. This is usually when the encoders indicatethe joint is within a specied distance from the destination (settable by the SETINTcommand). ATTN bus. This bus is similar to the INTTOL bus. A board asserts its ATTN line (activelow) when it has an error condition, or has detected a zero index when in hunt zero indexmode. The logical OR of all ATTN lines is available as the REQB signal of the arm interface.Figures 2.4 and 2.5 show details of the timing relationships involved in reading and writing tothe axis processors.2.1.5 Analog to digital converterThe AIB contains an ADC0816 16 channel 8-bit ADC for digitizing joint potentiometer signals.More modern Mark 1 controllers, including those built by Kawasaki, utilize a 10-bit converter.The ADC output is tri-stated onto the internal data bus when it is read, but only the low order8 or 10-bits are signicant.
The converter has a 100 s conversion time.13Joint 1data writtenJoint 0data writtenJoint 2data writtenCommandwrittenCSR0NDRWJCRLcommand latchedSELjoint 0joint 1joint 2CMD/XFER_REQNMIjoint 0interruptedjoint 1interruptedjoint 2interruptedservo data2 bytes of dataread by digital servo/XFER_ACKREQA/CTUPjoint addresscounter incrementedFigure 2.5: Timing details for vector mode writing.500ns/DATASTBData latched on this edge/XFER_ACKREQAFigure 2.6: Timing details of REQA handshake line. Note delay between REQA being asserted,and the second data byte being latched.When a READADC command is issued, the command is decoded by the AIB (U1B) whichinitiates conversion from the channel selected by the low order bits of the command word.The command is also given to the digital servo card which simply delays for a time beforeacknowledging.
When the host reads the data word it takes the output of the ADC not thecontent of the data latch.2.1.6 Communications bus timingFor a host reading data from the AIB there is a potential timing problem as shown in Figure 2.6.The second data byte is not in fact latched into the AIB until 500 ns after the REQA acknowledgesignal is given. This problem was not observed with early, slow, host computers. A fast hostshould introduce some delay after the rising edge of REQA before assuming that the data word14has been completely latched.We have measured that REQA rises around 75 s after the command has been issued. In thattime the 6503 has been interrupted, fetched the command, executed the appropriate handlerand read or written 2 bytes of host data.
Examination of the code reveals a number of criticalsections during which interrupts are masked out and this could conceivably increase the axisresponse time.Under some circumstances a rising edge on REQA may be caused for other reasons. If theprevious command was an AIB (SELECT7) operation REQA will be left in the low state. REQAis set when a digital servo board asserts XFER REQ.
It is cleared on (U3A, U2B and U6A):RESET + CSR0(NDR + DTRANS VECMODE)Thus an AIB operation will leave REQA deasserted; the data transfer will clear it, and since nodigital servo board is involved, it will not be set at completion of the operation.2.2 Digital Servo Card Operation2.2.1 The hardwareThe digital servo board uses a 6503, an 8-bit microprocessor clocked at 1 MHz (from a clock lineon the servo backplane) to close the axis position loop at approximately 1 kHz and to executecommands from the host, see Table 2.2. A 2716 EPROM contains up to 2kbytes of rmwareand a 6532 multifunction chip provides 128 bytes of RAM, a counter/timer, and some parallelinput/output capability.
The memory map for the 6503 based servo card is shown in Figure2.7. Other I/O facilities, detailed in Table 2.4, include: the AIB servo data bus for reading from and writing to the AIB; the host command bus; current, and index latched, encoder values.and are shown in Table 2.4.2.2.2 InterruptsThe 6503 axis processor receives the following interrupts: NMI whenever the axis processor is selected (SEL bus line asserted) and there is a validcommand on the CMD bus (/XFER REQ asserted).
NMI may be masked out via a controlregister bit during critical code sections. IRQ from the 6532 due to timer countdowns (clock tick), and the zero index signal viainput PA7 of the 6532 device (U4A).2.2.3 Control register (CR)The control register is an 8-bit output port, U2B, whose bits are described in Table 2.3. The6503 rmware can control the operation of the analog servo board by means of:/INTto enable integral action on the analog servo board;to enable current mode where the DAC output commands motor currentrather than motor velocity;/CURR MODE15/LSB SERVO MODEto enable high-gain position servo mode1;to enable the analog velocity loopcommunicate joint status information to the host:/SERVO ENABLEif the axis is within the specied position tolerance;ATTN if the axis requests attentionand mask out NMI interrupts during critical sections of codeTOLNMI ENABLE.2.2.4 Read multiplexerThe read multiplexer consists of devices U1B-1E on the joint digital servo card.
It multiplexesfour 8-bit data sources onto the 6503's data bus: Encoder up/down counter (U2C/D) Encoder counter latch (U3C) Current value of CR Host CMD bus2.2.5 Encoder interfaceThe quadrature encoder signals are buered and shaped on the analog servo board and passedvia the backplane to the digital servo board. A state machine (U5D and associated logic)generate a count and direction signal from the encoder data. The logic generates 4 pulsesper encoder line, so an n line encoder generates 4n pulses per revolution. An 8-bit up/downThis signal is not driven by the current 6503 rmware, and the analog servo board does not use the outputof the LSB servo amplier.10x1000EPROM2716(2k)0x800boardi/o0x4000x10065320x80RAM0x0Figure 2.7: Axis processor memory map.16Command Value Read/WriteDescriptionPOSMODE 0WCommand motion in position control modeCURMODE 0x08WCommand current directly (no positioncontrol)SPOSTL0x10WSet position tolerance, set the width of theband around the target point within whichthe axis will assert in tolerance signal.SETPOS0x18WSet position encounter valueCALIB0x20WCalibrateSETDC0x28WSet DC osetSETINT0x30WSet integration band toleranceSTDATA0x38WStore data to 6503 RAMSTOPMDE 0x40WEnter stop modeNOP0x48WDo-nothingNOP0x50WDo-nothingNOP0x58WDo-nothingREADPOS 0x60RRead position counterREADSTAT 0x68RRead 6503 joint status wordREADADC 0x70RRead ADC (joint potentiometer)DIAGREAD 0x78RRead from the 6503 RAM location pointed toby memory location 2 (set up by a previousSTDATA operation).Table 2.2: Axis processor commands.Bit Value001102204308410520640780MeaningNMI ENABLEATTN/SERVO ENABLE/INT/LSB SERVO ENABLE/CURRENT MODETOLTable 2.3: Control register bit denitions.counter (U2C/D) counts the encoder edges and its output is available to the 6503 via theread-multiplexer.
The counter has a range of only 256 encoder edges so every clock interval(924 s) the hardware counter is read and a 24-bit software counter updated. On encoder index(once per motor revolution) the output of the up/down counter is latched (U3C) and the 6503interrupted. This latched output is available to the 6503 via the read-multiplexer.The RAM location encmax contains the number of encoder counts between zero indices andis used by the rmware.
It is an 8-bit value which is interpreted as being oset 0x300. Theusual values are 0xe8 (0x3e8 = 1000) or 0x20 (0x320 = 800). The Kawasaki rmware seemsnot to require this constant.2.2.6 Digital to analog converterA DAC80 12-bit DAC is connected to the parallel output lines of the 6532 device. The bipolaroutput voltage is in the range -10 V to 9.995 V. This voltage is used to command the analog17NamebuslbushbuslakbushakctlwadcrAddress400401402403600601601602603OperationsrwrwrwrwrwwrrwrUsagelow byte of host data bushigh byte of host data buslo byte of host bus, assert /XFER ACKhi byte of host bus, assert /XFER ACKcounter loapparently unused signalencoder value latched at zero indexcontrol register (CR)host bus command/status byteTable 2.4: Digital servo board I/O addresses.velocity loop in position control mode, or the current loop in current control mode. The voltageis buered by a unity-gain op-amp stage on the digital board with feedback coming from theanalog board.
This is perhaps to counter the eect of voltage loss due to poor contacts betweenthe two servo boards.2.2.7 AIB data I/OFour locations are used by the 6503 to read/write data to the AIB. The locations busl or bushread or write data to the servo data bus and cause generation of the appropriate /HIBYTE and/DATASTB signals.
Reading or writing to the locations buslak or bushak has the same eect,but also asserts the end of operation handshake /XFER ACK and is used for the second (last)byte transferred.2.3 Digital servo board rmwareThe rmware revision level for our Mark I controller is 5.0, and the following sections describethe algorithms used.
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