Timequest (1162602), страница 3

Просмтор этого файла доступен только зарегистрированным пользователям. Но у нас супер быстрая регистрация: достаточно только электронной почты!

Текст из файла (страница 3)

from the Constraint menu. A window shown in Figure 17 will appear.Figure 17. TimeQuest window to create a clock constraint.In the figure the clock constraint is given the name clock in the top field. The clock period is assigned to be 4 ns inthe field below. The next two fields define the time at which the clock changes from 0 to 1 and 1 to 0. Leaving thesefields empty indicates that the rising edge of the clock should appear at time 0, and the falling edge at one half ofthe clock period.

Finally, the Targets field is set to the signal name clock as shown in the figure, to indicate that thegiven constraint is for the signal named clock. Pressing the Run button applies the constraint. The constraint can besaved into an SDC file by double-clicking on the Write SDC File... task as shown in Figure 18.Altera Corporation - University ProgramMay 201615U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0Figure 18. Saving a constraints file.Once the constraints file is saved, it can be used by Quartus Prime when compiling a project.

This is done inQuartus Prime by going into Assignments > Settings... > TimeQuest Timing Analyzer, and adding the SDC fileto the TimeQuest timing analyzer settings as shown in Figure 19. The Quartus Prime project can then be recompiledto use the constraint.Figure 19.

Including a constraints file in Quartus Prime project.16Altera Corporation - University ProgramMay 2016U SING T IME Q UEST T IMING A NALYZER6For Quartus Prime 16.0Circuits with Multiple Clock SignalsTimeQuest is capable of analyzing circuits that contain multiple clocks. This includes cases where the designeruses several clocks, or where clock signals are generated automatically to support features such as the SignalTapII Logic Analyzer or a JTAG interface. Should the reader work with such designs, it is important to note that theexperience with TimeQuest may differ from that described above. In designs with multiple clocks, it is importantto apply constraints to each clock before performing timing analysis.

Doing so will make the analyzer provide thesame reports as described in previous sections.7ConclusionThis tutorial demonstrated the basic use of the TimeQuest timing analyzer. While the descriptions of timing analysisand setting up timing constraints were limited to clock constraints in a simple circuit, TimeQuest provides even morepowerful tools to specify timing constraints for larger and more complex designs.Copyright ©2016 Altera Corporation.Altera Corporation - University ProgramMay 201617.

Характеристики

Список файлов семинаров