Timequest (1162602), страница 2
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TimeQuest adds a value of −0.002 ns to account for ClockUncertainty, leading to the final slack value of -2.486 ns.4.1Setting Up Timing Constraints for a DesignIn the TimeQuest GUI, select Constraints > Create Clock, which leads to the Create Clock window shown inFigure 8. Set the Clock name to clock and the Period to 4.000 ns. It is necessary to tell TimeQuest which signal inour design this clock constraint applies to. To do this, click the ... button to the right of the Targets field, leadingto the Name Finder window shown in Figure 9. Click List to show all of the ports in the design. In the list of ports,highlight clock, which is the clock signal in our circuit, press >, then click OK.
Finally, click the Run button in theCreate Clock window to apply the constraint.In order to use this clock constraint for all future compilations and timing analysis of this project, we must savethe constraint to a file of the type sdc which stands for Synopsys Design Constraint. This file uses an industrystandard format for specifying timing constraints. Select Constraints > Write SDC File... to write all of thecurrently set constraints (in our case just the one clock constraint) to an SDC file. This leads to the dialog shownin Figure 10. Specify the file name add_three_numbers.sdc and press OK.
Note that Quartus will by default try tolocate and use the sdc file whose file name matches the project name (except for the .sdc extension).You will notice that our clock timing report Setup clock is now out of date, as indicated by the yellow font andhighlighting. Right-click the report and select Regenerate, as shown in Figure 11, to re-run the timing analysisusing the new 4 ns clock period constraint. This analysis results in a positive slack of 0.514 ns. The correspondingwaveforms are depicted in Figure 12.Figure 8. The Create Clock window.8Altera Corporation - University ProgramMay 2016U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0Figure 9.
The Name Finder window.Figure 10. The Write SDC File dialog.Figure 11. Regenerating the Timing Report.Altera Corporation - University ProgramMay 20169U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0Figure 12. Timing analysis results using the 4 ns clock period constraint.Close the TimeQuest GUI. A dialog will appear, asking if you want to save the SDC file. Select No, since we havealready saved the SDC file.Since we have not recompiled the example design after adding the 4 ns clock period constraint, the timing analysisis based of the circuit that was produced by Quartus Prime when using the (default) 1 ns clock period constraint.To see the effect of the new timing constraint on the compilation results, recompile the project.
Then, follow thesteps described previously to perform a new timing analysis using TimeQuest. The 4 ns timing constraint will causethe Quartus Prime optimization algorithms to make different decisions from those made when the (default) 1 nsconstraint was used. In particular, the optimization algorithms will likely take less time to execute, because once thegenerated circuit has sufficient positive slack to meet the constraint, the algorithms can terminate. Figure 13 showsthe results of timing analysis, with a positive slack of 0.600 ns.10Altera Corporation - University ProgramMay 2016U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0Figure 13. Updated compilation results with the 4 ns clock period constraint.5The TimeQuest Graphical User InterfaceIn the above sections we accessed TimeQuest via the Quartus Prime Compilation Report.
Another way to openthe TimeQuest GUI is to use the command Tools > TimeQuest Timing Analyzer from the main Quartus Primewindow. The TimeQuest window shown in Figure 14, will appear.Altera Corporation - University ProgramMay 201611U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0Figure 14. TimeQuest window.To demonstrate some of the commands available in the TimeQuest GUI, we go through a set of basic steps toobtain timing data for the example design. In the Tasks pane, begin by double-clicking the Create Timing Netlistcommand to create a timing netlist, which will be used to perform the analysis. Note that while this netlist wasgenerated automatically when performing a timing analysis as described in the previous sections, the netlist can alsobe generated manually by using the Tasks pane. Next double-click Read SDC File to instruct the analyzer to reada Synopsys Design Constraints (SDC) file and apply the constraints during analysis.
The SDC file can be editedmanually (using any text editor) at any time, and the timing analysis can then be re-run using the new constraints.Finally, double-click the Update Timing Netlist command to use the specified constraints to determine which partsof the circuit fail to meet them. Once the timing netlist is updated, reports can be generated.5.1Timing Analysis ReportsTo generate a report, double-click on a report name in the Tasks pane.
For example, double-click on the ReportSetup Summary. This command will bring up a window in the view pane as shown in Figure 15. Right-clickon the clock name then click on Report Timing... to open the Report Timing dialog in Figure 16.
Although wepreviously showed this dialog in Figure 6 we now describe it in more detail.12Altera Corporation - University ProgramMay 2016U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0Figure 15. Setup summary.There are several fields in Figure 16 that help specify the data to be reported. The first field is the Clocks field,which specifies the types of paths that will be reported. More precisely, it specifies the clock signal at the sourceflip-flops (From clock) and the clock signal at the destination flip-flops (To clock).
For this example, choose thesignal named clock for the To clock and From clock fields. This will limit the reporting to the register-to-registerpaths only.Altera Corporation - University ProgramMay 201613U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0Figure 16. Timing report generation window.The next field is the Targets field. It can be used to refine the report by focusing only on certain paths in the design.We can specify the starting and the ending point of the paths of interest by filling the From and To fields. In addition,we can look at only the paths that pass through certain nodes in the design. For this example, we leave these fieldsblank to indicate that every path should be taken into account for the report.The next two fields are the Analysis type and Paths fields.
The Analysis type field specifies if the report shouldcontain setup, hold, recovery, or removal information. Each of these analyses looks for distinct timing characteristicsin your design. For example, the setup analysis determines if the data arrives at a flip-flop sufficiently early for theflip-flop to store it reliably, given a clock period. On the other hand, the hold analysis determines if the data inputat any given flip-flop remains stable after the positive edge of the clock long enough for the data to be stored in aflip-flop reliably. The Paths field specifies the maximum number of paths to be reported and the maximum slackrequired for a path to be included in the report. For this example, choose the type of analysis to be Setup and select10 paths to be reported.
This will generate a setup analysis report and show 10 paths with the least slack.The next set of fields specify the Output format and the level of detail in the report. The output could be to a window14Altera Corporation - University ProgramMay 2016U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0or a file. Set the Detail level to Path Only, then set the output to a window by checking the Report panel namecheck box (and not the File name check box).
The window should be named Setup: clock by default, and thatname will identify the report in the report pane.Finally, the last field is the Tcl command field. This field shows a command that will be executed to generate therequested report. You do not need to edit this field.5.2Creating Timing Constraints in the TimeQuest GUITiming constraints can be entered by using the Constraints menu in the TimeQuest GUI. To assign a clock constraint, select Create Clock...
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