Timequest (1162602)

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Using TimeQuestTiming AnalyzerFor Quartus Prime 16.01IntroductionThis tutorial provides an introduction to TimeQuest Timing Analyzer. It demonstrates how to set up timing constraints and obtain timing information for a logic circuit.The reader is expected to have a basic understanding of the Verilog hardware description language, and to be familiarwith the Altera Quartus Prime CAD software.Contents:• Introduction to timing analysis• Using TimeQuest• Setting Up Timing ConstraintsAltera Corporation - University ProgramMay 20161U SING T IME Q UEST T IMING A NALYZER2For Quartus Prime 16.0BackgroundTiming analysis is a process of analyzing delays in a logic circuit to determine the conditions under which the circuitoperates reliably.

One example of a timing analysis computation is to find the maximum clock frequency for acircuit, illustrated in Figure 1.aDQ1 nsbDDQfQ1 nscDQ1 nsdDQclockFigureD1.QA example for timing analysis.a1 nsQ drive a combinational circuit that generates an output that is laterDbIn this example, flip-flops on the left-handsidestored in the flip-flop on the right-hand side. To operate correctly, the clock period has to be long enough to acD Q1 nsfcommodate the delay on the longest path in the circuit. If we assume that the clock-to-Q and setup times for eachcQflip-flop are 1 ns, and the delay through eachD gateis 1 ns, then the maximum clock frequency for this circuit is:f max=d1 ns11== 200 MHzt cDq + 3 × t and + t su 5 nsQComputing the longest delays in aclockcircuit and comparing these delays to the clock period is a basic function of atiming analyzer. The timing analyzer can be used to guide computer-aided design (CAD) tools in the implementationof logic circuits.

For example, the circuit in Figure 1 shows an implementation of a 4-input function using 2-inputAND gates. Without any timing requirements, the presented solution is acceptable. However, if a user requiresthe circuit to operate at a clock frequency of 250 MHz, then the above solution is inadequate. By placing timingconstraints on the maximum clock frequency, it is possible to direct the CAD tools to seek an implementation thatmeets those constraints.

As a result, the CAD tools may arrive at a solution shown in Figure 2. The new circuit hasf max = 250 MHz and thus meets the required timing constraints.2Altera Corporation - University ProgramMay 2016cDQ1 nsdDQU SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0clockaDQ1 nsbDQDQ1 nscDQf1 nsdDQclockFigure 2. Functionally equivalent circuit with a different logic structure.In this tutorial, we demonstrate how to obtain timing information and how to set timing constraints using the TimeQuest timing analyzer.The example circuit provided with this tutorial contains only one clock signal, which is connected to all flip-flops.Performing timing analysis for circuits that have multiple clock signals is discussed in section 6.3Design ExampleAs an example we will use an adder that adds three 8-bit numbers and produces a sum output.

The inputs are A , B ,and C , which are stored in registers reg_A, reg_B and reg_C at the positive edge of the clock. The three registersprovide inputs to the adder, whose result is stored in the reg_sum register. The output of the reg_sum register drivesthe output port sum. The diagram of the circuit is shown in Figure 3.reg_AA8D Q+reg_BB8D Qreg_sum+D Q10sumreg_CC8D QclockFigure 3. Diagram of the example circuit.Altera Corporation - University ProgramMay 20163U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0The Verilog source code for the design is given in Figure 4. Note that the ”synthesis keep” comment is included inthis code. This comment is interpreted as a directive that instructs the Quartus Prime software to retain the specifiednodes in the final implementation of the circuit and keep their names as stated. This directive will allow us to referto these nodes in the tutorial.module add_three_numbers(clock, A, B, C, sum);input clock;input [7:0] A,B,C;output [9:0] sum;// Registersreg [7:0] reg_A, reg_B, reg_C /* synthesis keep */;reg [9:0] reg_sum /* synthesis keep */;always @(posedge clock)beginreg_A <= A;reg_B <= B;reg_C <= C;reg_sum <= reg_A + reg_B + reg_C;endassign sum = reg_sum;endmoduleFigure 4.

Verilog code for the example circuit.To begin the tutorial create a new Quartus Prime project for the design of our example circuit. Select as the targetdevice the EP4CE115F29C7, which is the FPGA chip on the Altera DE2-115 board. Type the Verilog code inFigure 4 into a file and add this file to the project.You do not need to make any pin assignments for this example.

Compile the project to see the results of timinganalysis. These results will be available in the compilation report, once the design is compiled.4Using TimeQuestAs illustrated in Figure 5, open the Timequest Timing Analyzer section of the Compilation Report, and click on theClocks item to select it.

In the Clocks display panel that opens on the right-hand side of the Quartus Prime window,notice that the clock signal from the example design has been given a clock period constraint of 1 ns (frequency of1000 MHz). This is a default constraint that the Quartus Prime CAD tool places on any clock signal in a designproject that does not have any user-provided timing constraints.4Altera Corporation - University ProgramMay 2016U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0Figure 5. The Timequest section of the compilation report.As indicated in Figure 5, right-click on the name of the clock signal and select the command Report Timing ...

(InTimequest UI). This action opens the Report Timing dialog shown in Figure 6. Click the drop-down arrow in theFrom clock item and select the clock signal. This selection is used to instruct TimeQuest to analyze all paths in theexample circuit that start and end at flip-flops that are clocked by the clock signal. The various settings displayed inFigure 6 are described in Section 5.Accept all of the other default selections in Figure 6 and click on the Report Timing button. This command opensthe Timequest Graphical User Interface (GUI), as depicted in Figure 7.Altera Corporation - University ProgramMay 20165U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0Figure 6.

The Report Timing dialog.6Altera Corporation - University ProgramMay 2016U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0Figure 7. The TimeQuest GUI.The TimeQuest GUI consists of several sections. They include the main menu at the top, the Report pane in thetop-left corner, the Tasks pane on the left, the detailed results panes in the middle, and the Console display at thebottom of the window. The main menu is used to interact with the TimeQuest tool and issue commands.

The Reportpane contains any reports generated when using the tool, and the Tasks pane contains a sequence of actions that canbe performed to obtain timing reports. The View pane hosts any windows that are opened, such as details about thetiming information. The Console window at the bottom provides access to a command line for TimeQuest.We will focus on the panes in the middle of the TimeQuest GUI, which show detailed results of the timing analysis.The Slow 1200mV 85C Model pane lists the analyzed paths in the circuit from source to destination flip-flopsfor that particular timing model. The first column in this pane shows the Slack of each path with respect to the(default) clock constraint of 1 ns. For each path in the circuit the slack value represents the difference between theclock period constraint and the path delay; a positive slack means that the delay is smaller than the constraint, anda negative slack represents a delay that is larger than the constraint.

The slack values in the report are negative, andshown in red, because the timing results fail to meet the required constraint. The maximum negative slack valueshown is -2.486 ns, which means that the worst-case delay path is 1 − (−2.486) = 3.486 ns long. This corresponds toa maximum usable clock frequency, Fmax , of about 286.86 MHz.The waveforms shown for path #1 in Figure 7 illustrate the detailed timing situation. The waveforms show that theclock signal takes 3.058 ns to propagate from its input pin to the source flip-flop, and then this flip-flop produces datathat takes 3.402 ns to reach the destination flip-flop.

Also, the clock signal takes 2.944 ns to reach the destination flipflop. The clock delays at the source and destination flip-flops represent a clock skew t skew = 2.944−3.058 = −0.114.Altera Corporation - University ProgramMay 20167U SING T IME Q UEST T IMING A NALYZERFor Quartus Prime 16.0A value of 0.032 to account for Clock Pessimism is added to the clock skew, making the final clock skew value to be-0.082 ns. The difference in the required arrival time of the data on this path and the actual arrival time is shown bythe negative slack value of 1 − 3.402 + t skew = −2.484 ns.

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