Using_ModelSim (1162592), страница 4
Текст из файла (страница 4)
The tool name is a drop-down list containing the names of simulation tools forwhich Quartus Prime can produce a netlist with timing information automatically. This list contains many wellknown simulation tools, including ModelSim. From the drop-down list select ModelSim-Altera.Once a simulation tool is selected, EDA Netlist Writer settings become available.
These settings configure QuartusPrime to produce input for the simulation tool. Quartus Prime will use these parameters to describe an implementeddesign using a given HDL language, and annotate it with delay information obtained after compilation. The settingswe can define are the HDL language, simulation time scale that defines time step size for the simulator to use, thelocation where the writer saves design and delay information, and others. Set these settings to match those shown inFigure 24 and click OK.With the EDA Tools Settings specified, we can proceed to compile the project in Quartus Prime. The compilationprocess synthesizes, places, and routes the design, and performs timing analysis.
Then it stores the compilationresult in the simulation directory for ModelSim to use. Take a moment to examine the files generated for simulationusing a text editor. The two main files are serial.vo, and serial_v.sdo.The serial.vo file is a Verilog file for the design. The file looks close to the original Verilog file, except that thedesign now contains a wide array of modules with a cycloneive_ prefix. These modules describe resources on anAltera Cyclone IV E FPGA, on which the design was implemented using lookup tables, flip-flops, wires and I/Oports. The list of delays for each module instance in the design is described in the serial_v.sdo file.22Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 24.
Quartus Prime EDA simulation tool settings.5.2Running a Timing SimulationTo simulate the design using timing simulation we must create a ModelSim project. The steps are the same as inthe previous section; however, the project is located in the example/timing/simulation/modelsim subdirectory, andthe source file is serial.vo. We do not need to include the serial_v.sdo file in the project, because a reference to itis included in the serial.vo file.
Once you added the source file to the project, compile it by selecting Compile >Compile All.The next step in the simulation procedure is to place the ModelSim software in simulation mode. In the previoussection, we did this by selecting Simulate > Start Simulation..., and specifying the project name. To run a timingsimulation there is an additional step required to include the Altera Verilog library and Altera Cyclone IV E devicelibrary in the simulation. The Cyclone IV E device library library contains information about the logical operationof modules with the cycloneive_ prefix. To include the Modelsim libraries in the project, select Simulate > StartSimulation... and select the Libraries tab as shown in Figure 25.Altera Corporation - University ProgramMay 201623U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 25. Including Altera Cyclone IV E library in ModelSim project.The Altera Cyclone IV E library is located in the altera/verilog/cycloneive directory in the ModelSim-Altera software.
To add this library to your project, select Add... and choose cycloneive_ver from the dropdown list. Alsoadd the altera_ver library to the project in the same way. Then, click on the Design tab, select your project forsimulation (tutorial > serial), and click OK.When the ModelSim software enters simulation mode, you will see a significant difference in the contents of theworkspace tabs on the left-hand side of the window as compared to when you ran the functional simulation. Inparticular, notice the sim tab and the Objects window shown in Figure 26. The list of modules in the sim tab islarger, and the objects window contains more signals. This is due to the fact that the design is constructed usingcomponents on an FPGA and is more detailed in comparison to an abstract description we used in the previoussection of the tutorial.24Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 26.
Workspace tabs and Objects window for timing simulation.We simulate the circuit by creating a waveform that includes signals sum, A, B, start (go), and resetn aliases asbefore. In addition, we include the clock, reg_sum|q, reg_A|q, and reg_B|q signals from the Objects window.Signals reg_A|q and reg_B|q are registers that store A and B at the positive edge of the clock. The reg_sum|q signalis a register that stores the resulting sum.Begin the simulation by resetting the circuit. To do this, set the go and resetn signals to 0. Also, set the clock inputto have a period of 20 ns, whose first edge is a falling edge. To run the simulation, set the simulation step to 20 nsand press the Run button.
The simulation result is shown in Figure 27.Altera Corporation - University ProgramMay 201625U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 27. Timing Simulation after 20 ns.To proceed with the simulation deassert the resetn signal by setting it to 1, and apply data to inputs A and B. Setthem to 143 and 57, and assign a value of 1 to the go input as described in the Functional Simulation section of thetutorial. Then run the simulation for a period of 20 ns, by pressing the Run button.
The simulation result is shownin Figure 28. Remember to change the radix of A, B, sum, and their corresponding registers to unsigned.26Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 28. Timing Simulation after 40 ns.In Figure 28 the data is stored in registers reg_A|q and reg_B|q at the positive edge of the clock. Notice that thesimulation indicated that the data in those registers changes some time after the positive edge of the clock, unlike inthe functional simulation. The reason for this difference are the delays in the circuit.
We can use the zoom buttonsto see this more clearly.When we zoom in on the time when registers reg_A|q and reg_B|q change value, we see the register values changeas shown in Figure 29. In the figure, register reg_B|q stabilizes on a value of 57 at time 33296 ps. This is 3296 psafter the positive edge of the clock appeared at the clock input. Part of the difference in times between the clock edgeand the change of data in register reg_B|q comes from the fact that the clock signal must travel from the input pinon the FPGA device to the registers. The other part of the time is due to the clock-to-Q time of the register, which isthe time it takes for a register to change output after it sees a positive edge on the clock input.Altera Corporation - University ProgramMay 201627U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 29.
Zoomed-in Timing Simulation after 40ns.Another interesting aspect of the timing simulation can also be observed in Figure 29. Notice that register reg_A|qfirst changes value to 15 and a few picoseconds later assumes the value 143. This is because the clock signal doesnot get to every flip-flop at exactly the same time - this is called clock skew.6Concluding RemarksThis tutorial discussed the basic use of ModelSim simulator.
We demonstrated how to perform a functional simulation using a user-written Verilog code, as well as a detailed timing simulation. For the timing simulation, wepresented a simple method to generate design description using Altera Quartus Prime CAD software, which includes the low-level design details and circuit delays.There are more advanced options for simulation available in ModelSim software.
They can help automate and speedup the simulation of larger more complex designs. These features are covered in the tutorials provided with theModelSim tool, and are beyond the scope of this introductory tutorial.28Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Copyright ©1991-2016 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, thestylized Altera logo, specific device designations, and all other words and logos that are identified as trademarksand/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in theU.S.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
