Using_ModelSim (1162592)
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Using ModelSim to Simulate LogicCircuits in Verilog DesignsFor Quartus Prime 16.01IntroductionThis tutorial is a basic introduction to ModelSim, a Mentor Graphics simulation tool for logic circuits. We show howto perform functional and timing simulations of logic circuits implemented by using Quartus Prime CAD software.The reader is expected to have the basic knowledge of the Verilog hardware description language, and the AlteraQuartus® Prime CAD software.Contents:• Introduction to simulation• What is ModelSim?• Functional simulation using ModelSim• Timing simulation using ModelSimAltera Corporation - University ProgramMay 20161U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNS2For Quartus Prime 16.0BackgroundDesigners of digital systems are inevitably faced with the task of testing their designs.
Each design can be composedof many modules, each of which has to be tested in isolation and then integrated into a design when it operatescorrectly.To verify that a design operates correctly we use simulation, which is a process of testing the design by applyinginputs to a circuit and observing its behavior. The output of a simulation is a set of waveforms that show how acircuit behaves based on a given sequence of inputs.
The general flow of a simulation is shown in Figure 1.Figure 1. The simulation flow.There are two main types of simulation: functional and timing simulation. The functional simulation tests the logicaloperation of a circuit without accounting for delays in the circuit. Signals are propagated through the circuit usinglogic and wiring delays of zero. This simulation is fast and useful for checking the fundamental correctness of the2Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0designed circuit.The second step of the simulation process is the timing simulation.
It is a more complex type of simulation, wherelogic components and wires take some time to respond to input stimuli. In addition to testing the logical operation ofthe circuit, it shows the timing of signals in the circuit. This type of simulation is more realistic than the functionalsimulation; however, it takes longer to perform.In this tutorial, we show how to simulate circuits using ModelSim. You will need the Quartus Prime CAD softwareand the ModelSim software, or ModelSim-Altera software that comes with Quartus Prime, to work through thetutorial.3Example DesignOur example design is a serial adder.
It takes 8-bit inputs A and B and adds them in a serial fashion when the startinput is set to 1. The result of the operation is stored in a 9-bit sum register.A block diagram of the circuit is shown in Figure 2. It consists of three shift registers, a full adder, a flip-flop to storecarry-out signal from the full adder, and a finite state machine (FSM). The shift registers A and B are loaded withthe values of A and B. After the start signal is set high, these registers are shifted right one bit at a time. At the sametime the least-significant bits of A and B are added and the result is stored into the shift register sum.
Once all bits ofA and B have been added, the circuit stops and displays the sum until a new addition is requested.Figure 2. Block diagram of a serial-adder circuit.The Verilog code for the top-level module of this design is shown in Figure 3. It consists of the instances of the shiftregisters, an adder, and a finite state machine (FSM) to control this design.Altera Corporation - University ProgramMay 20163U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNS1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17.18.19.20.21.22.23.24.25.26.27.28.29.30.31.32.33.34.35.36.For Quartus Prime 16.0module serial(A, B, start, resetn, clock, sum);input [7:0] A, B;input resetn, start, clock;output [8:0] sum;// Registerswire [7:0] A_reg,B_reg;reg cin;// Wireswire reset, enable, load;wire bit_sum, bit_carry;// Control FSMFSM my_control(start, clock, resetn, reset, enable, load);// Datapathshift_reg reg_A( clock, 1'b0, A, 1'b0, enable, load, A_reg);shift_reg reg_B( clock, 1'b0, B, 1'b0, enable, load, B_reg);// a full adderassign {bit_carry, bit_sum} = A_reg[0] + B_reg[0] + cin;always @(posedge clock)beginif (enable)if (reset)cin <= 1'b0;elsecin <= bit_carry;endshift_reg reg_sum( clock, reset, 9'd0, bit_sum, enable, 1'b0, sum);defparam reg_sum.n = 9;endmoduleFigure 3.
Verilog code for the top-level module of the serial adder.The Verilog code for the FSM is shown in Figure 4. The FSM is a 3-state Mealy finite state machine, where the firstand the third state waits for the start input to be set to 1 or 0, respectively.
The computation of the sum of A and B4Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0happens during the second state, called WORK_STATE. The FSM completes computation when the counter reachesa value of 8, indicating that inputs A and B have been added. The state diagram for the FSM is shown in Figure 5.1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17.18.19.20.21.22.23.24.25.26.27.28.29.30.31.32.33.34.35.module FSM(start, clock, resetn, reset, enable, load);parameter WAIT_STATE = 2'b00, WORK_STATE = 2'b01, END_STATE = 2'b11;input start, clock, resetn;output reset, enable, load;reg [1:0] current_state, next_state;reg [3:0] counter;// next state logicalways@(*)begincase(current_state)WAIT_STATE:if (start) next_state <= WORK_STATE;else next_state <= WAIT_STATE;WORK_STATE:if (counter == 4'd8) next_state <= END_STATE;else next_state <= WORK_STATE;END_STATE:if (~start) next_state <= WAIT_STATE;else next_state <= END_STATE;default: next_state <= 2'bxx;endcaseend// state registers and a counteralways@(posedge clock or negedge resetn)beginif (~resetn)begincurrent_state <= WAIT_STATE;counter = 'd0;endelsebeginFigure 4.
Verilog code for the FSM to control the serial adder (Part a).Altera Corporation - University ProgramMay 20165U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNS36.37.38.39.40.41.42.43.44.45.46.47.For Quartus Prime 16.0current_state <= next_state;if (current_state == WAIT_STATE)counter <= 'd0;else if (current_state == WORK_STATE)counter <= counter + 1'b1;endend// Outputsassign reset = (current_state == WAIT_STATE) & start;assign load = (current_state == WAIT_STATE) & start;assign enable = load | (current_state == WORK_STATE);endmoduleFigure 4. Verilog code for the FSM to control the serial adder (Part b).Figure 5.
State diagram.The Verilog code for the shift register is given in Figure 6. It consists of synchronous control signals to allow data tobe loaded into the shift register, or reset to 0. When enable input is set to 1 and the data is not being loaded or reset,the contents of the shift register are moved one bit to the right (towards the least-significant bit).6Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNS1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17.18.19.20.21.22.23.24.For Quartus Prime 16.0module shift_reg( clock, reset, data, bit_in, enable, load, q);parameter n = 8;input clock, reset, bit_in, enable, load;input [n-1:0] data;output reg [n-1:0] q;always@(posedge clock)beginif (enable)if (reset)q <= 'd0;elsebeginif (load)q <= data;elsebeginq[n-2:0] <= q[n-1:1];q[n-1] <= bit_in;endendendendmoduleFigure 6.
Verilog code for the shift register.The design is located in the example/functional and example/timing subdirectories provided with this tutorial. AQuartus Prime project for this design has been created as well.In the following sections, we use the serial adder example to demonstrate how to perform simulation using ModelSim. We begin by describing a procedure to perform a functional simulation, and then discuss how to perform atiming simulation.4Functional Simulation with ModelSimWe begin this tutorial by showing how to perform a functional simulation of the example design. We start by openingthe ModelSim program.Altera Corporation - University ProgramMay 20167U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 7. ModelSim window.The ModelSim program window, shown in Figure 7, consists of three sections: the main menu at the top, a set ofworkspace tabs, and a command prompt at the bottom.
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