Using_ModelSim (1162592), страница 3
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It is the ability to combinesignals and create aliases. It is useful when signals of interest are not named as well as they should be, or thegiven names are inconvenient for the purposes of simulation. In this example, we rename the start signal to go byhighlighting the start signal and selecting Tools > Combine Signals.... The window in Figure 15 will appear.Figure 15.
Combine signals window.In the text field labeled Result name type go and press the OK button. This will cause a new signal to appear in thesimulation window. It will be named go, but it will have an orange diamond next to its name to indicate that it is analias. Once the go alias is created, the original start input is no longer needed in the simulation window, so removeit by highlighting it and pressing the delete key.
Your simulation window should now look as in Figure 16.14Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 16. Simulation window with aliased signals.Now that we set up a set of signals to observe we can begin simulating the circuit. There are two ways to runa simulation in ModelSim: manually or by using scripts. A manual simulation allows users to apply inputs andadvance the simulation time to see the results of the simulation in a step-by-step fashion.
A scripted simulationallows the user to create a script where the sequence of input stimuli are defined in a file. ModelSim can read the fileand apply input stimuli to appropriate signals and then run the simulation from beginning to end, displaying resultsonly when the simulation is completed. In this tutorial, we perform the simulation manually.In this simulation, we use a clock with a 100 ps period. At every negative edge of the clock we assign new valuesto circuit inputs to see how the circuit behaves.
To set the clock period, right-click on the clock signal and selectClock... from the pop-up menu. In the window that appears, set the clock period to 100 ps and the first edge to bethe falling edge, as shown in Figure 17. Then click OK.Altera Corporation - University ProgramMay 201615U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 17. Set the clock period.We begin the simulation by resetting the circuit.
To reset the circuit, set the resetn signal low by right-clicking on itand selecting the Force... option from the pop-up menu. In the window that appears, set Value to 0 and click OK.In a similar manner, set the value of the go signal to 0. Now that the initial values for some of the signals are set, wecan perform the first step of the simulation. To do this, locate the toolbar buttons shown in Figure 18.Figure 18. Simulation control buttons on the toolbar.The toolbar buttons shown in Figure 18 are used to step through the simulation.
The left-most button is the restartbutton, which causes the simulation window to be cleared and the simulation to be restarted. The text field, shownwith a 100 ps string inside it, defines the amount of time that the simulation should run for when the Run button (tothe right of the text field) is pressed. The remaining three buttons, Continue, Run -All and Break, can be used toresume, start and interrupt a simulation, respectively. We will not need them in this tutorial.To run a simulation for 100 ps, set the value in the text field to 100 ps and press the Run button.
After the simulationrun for 100 ps completes, you will see the state of the circuit as shown in Figure 19. You can change the time scaleof your waveform by going to View > Zoom > Zoom Range.... Change the end time to 1200 ps and press OK.16Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 19.
Simulation results after 100 ps.In the figure, each signal has a logic state. The first two signals, A and B, are assigned a value between 0 and 1 in ablue color. This value indicates high impedance, and means that these signals are not driven to any logic state.
Thego and resetn signals are at a logic 0 value thereby resetting the circuit. The clock signal toggles state every 50 ps,starting with a falling edge at time 0, a rising edge at time 50 ps and another falling edge at 100 ps.Now that the circuit is reset, we can begin testing to see if it operates correctly for desired inputs. To test the serialadder we will add numbers 143 and 57, which should result in a sum of 200. We can set A and B to 143 and 57,respectively, using decimal notation.
To specify a value for A in decimal, right-click on it, and choose Force...from the pop-up menu. Then, in the Value field put 10#143. The 10# prefix indicates that the value that follows isspecified in decimal. Similarly, set the Value field of B to 10#57.To see the decimal, rather than binary, values of buses in the waveform window we need to change the Radix of Aand B to unsigned. To change the radix of these signals, highlight them in the simulation window and select Format> Radix > Unsigned, as shown in Figure 20. Change the radix of the sum signal to unsigned as well.Altera Corporation - University ProgramMay 201617U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 20.
Changing the radix of A, B and sum signals.Now that inputs A and B are specified, set resetn to 1 to stop the circuit from resetting. Then set go to 1 to beginserial addition, and press the Run button to run the simulation for another 100 ps. The output should be as illustratedin Figure 21. Notice that the values of inputs A and B are shown in decimal as is the sum. The circuit also recognizeda go signal and moved to state 01 to begin computing the sum of the two inputs.18Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 21. Simulation results after 200 ps.To complete the operation, the circuit will require 9 clock cycles. To fast forward the simulation to see the result,specify 900 ps in the text field next to the run button, and press the run button. This brings the simulation to time1100 ps, at which point a result of summation is shown on the sum signal, as illustrated in Figure 22.Altera Corporation - University ProgramMay 201619U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 22.
Simulation results after 1100 ps.We can see that the result is correct and the finite state machine controlling the serial adder entered state 11, inwhich it awaits the go signal to become 0. Once we set the go signal to 0 and advance the simulation by 100 ps, thecircuit will enter state 00 and await a new set of inputs for addition.
The simulation result after 1200 ps is shown inFigure 23.20Altera Corporation - University ProgramMay 2016U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0Figure 23. Simulation results after 1200 ps.At this point, we can begin the simulation for a new set of inputs as needed, repeating the steps described above. Wecan also restart the simulation by pressing the restart button to begin again from time 0.By using the functional simulation we have shown that the serial.v file contains an accurate Verilog HDL descriptionof a serial adder. However, this simulation did not verify if the circuit implemented on an FPGA is correct. Thisis because we did not use a synthesized, placed and routed circuit as input to the simulator. The correctness of theimplementation, including timing constraints can be verified using timing simulation.5Timing Simulation with ModelSimTiming simulation is an enhanced simulation, where the logical functionality of a design is tested in the presence ofdelays.
Any change in logic state of a wire will take as much time as it would on a real device. This forces the inputsto the simulation be realistic not only in terms of input values and the sequence of inputs, but also the time when theinputs are applied to the circuit.For example, in the previous section we simulated the sample design and used a clock period of 100 ps. This clockperiod is shorter than the minimum clock period for this design, and hence the timing simulation would fail toproduce the correct result.
To obtain the correct result, we have to account for delays when running the simulationand use a clock frequency for which the circuit operates correctly.Altera Corporation - University ProgramMay 201621U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus Prime 16.0For Altera FPGA-based designs the delay information is available after the design is synthesized, placed and routed,and is generated by Quartus Prime CAD software. The project for this part of the tutorial has been created for youin the example/timing subdirectory; it has been configured to work with the DE2-115 board.Note: timing simulations are only supported by Cyclone IV and Stratix IV devices.5.1Setting up a Quartus Prime Project for Timing Simulation with ModelSimTo perform timing simulation we need to set up Quartus Prime software to generate the necessary delay informationfor ModelSim by setting up EDA Tools for simulation in the Quartus Prime project.To set up EDA Tools for simulation, open the Quartus Prime project in example/timing subdirectory, and selectAssignment > Settings....
A window shown in Figure 24 will appear. The window consists of a list on the lefthand side to select the settings category and a window area on the right-hand side that displays the settings for agiven category. Select Simulation from the EDA Tool Settings category to see the screen shown on the right-handside of Figure 24.The right-hand side of the figure contains the tool name at the top, EDA Netlist Writer settings in the middle, andNativeLink settings at the bottom.
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