Диссертация (1150736), страница 27
Текст из файла (страница 27)
2005. Vol. 52, no. 5. P. 911–919.1708. Hegland M. A Self-sorting In-place Fast Fourier Transform Algorithm Suitablefor Vector and Parallel Processing // Numer. Math. Secaucus, NJ, USA, 1994.oct. Vol. 68, no. 4. P. 507–547. URL: "http://dx.doi.org/10.1007/s002110050074".9. Ammar G. S., Gragg W. B., Solvers T. The Generalized Schur Algorithm forthe Superfast Solution of Toeplitz Systems // in Rational Approximation andits Applications in Mathematics and Physics. Springer, 1987.
P. 315–330.10. В.В.Воеводин Е.Е.Тыртышников. Вычислительные процессы с теплицевыми матрицами. М.: Наука, 1987. с. 320.11. Салищев С.И. Вычислительные аспекты компенсации акустического эха //Гироскопия и навигация. 2005. № 1. с. 90.12. Салищев С.И. Быстрый алгоритм Шура в задаче подавления акустического эха // Вестник молодых ученых. Серия: прикладная математика имеханика. 2005. Т.
3. С. 77–87.13. Салищев С.И. Кусочно-полиномиальная аппроксимация с сокращеннымитаблицами и гарантированной точностью // Компьютерные инструментыв образовании. 2012. № 5. С. 3–10.14. Салищев С.И. Шеин Р.Е. Новые алгоритмы для конвейерного вычисления БПФ по смешанному основанию без копирования на многобанковойпамяти с произвольным доступом // Компьютерные инструменты в образовании. 2013.
№ 2. С. 18–30.15. Echo Compensation by Equalizer with Precise Spectrum Estimation /S. I. Salischev, A. E. Barabanov, K. M. Putyakov et al. // Audio Engineering Society Conference: 21st International Conference: ArchitecturalAcoustics and Sound Reinforcement. 2002. Jun. URL: http://www.aes.org/elib/browse.cfm?elib=11191.16.
S. S. Computational aspects of real-time acoustic echo cancellation // 7th international conference: Computer data analysis and modeling. Vol. 2. 2004.P. 146–149.17117. Салищев С.И. Ушаков Д.С. Использование языков и сред управляемогоисполнения для системного программирования // Системное программирование. 2009. Т. 4. С. 198–216.18. The Moxie JVM experience. Technical Report TRCS-08-01: Tech. Rep.: /S. I. Salishev, S. M. Blackburn, M. Danilov et al.: Australian National University, Department of Computer Science, 2008.
Jan.19. Demystifying Magic: High-level Low-level Programming / S. I. Salishev,D. Frampton, S. M. Blackburn et al. // Proceedings of the 2009 ACMSIGPLAN/SIGOPS International Conference on Virtual Execution Environments.VEE ’09.New York, NY, USA: ACM, 2009.P. 81–90. URL:http://doi.acm.org/10.1145/1508293.1508305.20. Static analysis method for deadlock detection in SystemC designs / S. Salishev,M. Moiseev, A. Zakharov et al. // System on Chip (SoC), 2011 InternationalSymposium on. 2011.
Oct. P. 42–47.21. Salishev S., Glukhikh M., Moiseev M. A Static Analysis Approach for Verification of Synchronization Correctness of SystemC Designs // Proceedingsof the 2013 Euromicro Conference on Digital System Design. DSD ’13.Washington, DC, USA: IEEE Computer Society, 2013.P. 89–96. URL:http://dx.doi.org/10.1109/DSD.2013.17.22.
Salishev S. Continuous-flow conflict-free mixed-radix fast fourier transform inmulti-bank memory. 2014. jul. WO Patent App. PCT/IB2013/000,446. URL:http://google.com/patents/WO2014108718A1.23. A novel ASIC design approach based on a new machine paradigm /R. W. Hartenstein, A. G.
Hirschbiel, M. Riedmuller et al. // Solid-State Circuits, IEEE Journal of. 1991. Vol. 26, no. 7. P. 975–989.24. G E. Latched carry save adder circuit for multipliers. 1967. sep. US Patent3,340,388. URL: http://www.google.com/patents/US3340388.25. Wallace C. A Suggestion for a Fast Multiplier // Electronic Computers, IEEETransactions on. 1964. Feb. Vol.
EC-13, no. 1. P. 14–17.17226. BOOTH A. D. A SIGNED BINARY MULTIPLICATION TECHNIQUE // TheQuarterly Journal of Mechanics and Applied Mathematics. 1951. Vol. 4, no. 2.P. 236–240. URL: http://qjmam.oxfordjournals.org/content/4/2/236.abstract.27. B R. Simultaneous carry adder.1960. dec.US Patent 2,966,305. URL:http://www.google.com/patents/US2966305.28. Ladner R. E., Fischer M.
J. Parallel prefix computation // Journal of the ACM(JACM). 1980. Vol. 27, no. 4. P. 831–838.29. Power-efficient system design / P. R. Panda, B. Silpa, A. Shrivastava et al.Springer, 2010.30. Sherazi Y. Design Space Exploration of Digital Circuits for Ultra-low EnergyDissipation. Ph.D. thesis: Lund University. 2013.31.
Bringing Network-on-Chip links to 45nm / M. Ferraresi, G. Gobbo, D. Ludovici et al. // System on Chip (SoC), 2011 International Symposium on. 2011.Oct. P. 122–127.32. IEEE Std 1666 - 2005 IEEE Standard SystemC Language Reference Manual.2006.33. Amdahl G. M. Validity of the Single Processor Approach to Achieving LargeScale Computing Capabilities // Proceedings of the April 18-20, 1967, SpringJoint Computer Conference. AFIPS ’67 (Spring). New York, NY, USA: ACM,1967. P. 483–485. URL: http://doi.acm.org/10.1145/1465482.1465560.34.
Woo D. H., Lee H.-H. S. Extending Amdahl’s Law for Energy-Efficient Computing in the Many-Core Era // Computer. Los Alamitos, CA, USA, 2008. dec.Vol. 41, no. 12. P. 24–31. URL: http://dx.doi.org/10.1109/MC.2008.494.35. Gustafson John L. Reevaluating Amdahl’s Law // Communications of theACM. 1988. Т. 31. С. 532–533.36. T. Grötker E. M., Mauss O. Evaluation of HW/SW Tradeoffs Using BehavioralSynthesis // Proc. Int. Conf. on Signal Processing Application and Technology(ICSPAT). Boston: 1996.
oct.17337. Open SystemC Initiative. SystemC Synthesizable Subset Draft 1.4: Tech.Rep.: : IEEE, 2009. URL: "http://www.accellera.org/images/downloads/drafts-review/SystemC_Synthesis_Subset_Draft_1_4.pdf".38. Calypto. Catapult C Synthesis."[Online; accessed 20-Sep-2016]".
URL:"https://www.mentor.com/hls-lp/".39. Cadence. C-to-Silicon Compiler."[Online; accessed 20-Sep-2016]". URL:"http://www.cadence.com/products/sd/silicon_compiler/pages/default.aspx".40. Cadence. Cynthesizer. "[Online; accessed 20-Sep-2016]". URL: "https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/system-design-verification/cynthesizer-solutioon-ds.pdf".41.
Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs. / A. Nayak, M. Haldar, A. N. Choudhary et al. //DATE. 2001. P. 722–728. URL: "http://dblp.uni-trier.de/db/conf/date/date2001.html#NayakHCB01".42. Shi C., Brodersen R. W. Automated fixed-point data-type optimization toolfor signal processing and communication systems. // DAC / Ed. by S. Malik,L. Fix, A. B.
Kahng. ACM, 2004. P. 478–483. URL: "http://dblp.uni-trier.de/db/conf/dac/dac2004.html#ShiB04".43. Stephenson M., Babb J., Amarasinghe S. P. Bitwidth analysis with application to silicon compilation. // PLDI / Ed. by M. S. Lam. ACM, 2000.P. 108–120. URL: "http://dblp.uni-trier.de/db/conf/pldi/pldi2000.html#StephensonBA00".44. Automatic Conversion of Floating Point MATLAB Programs into FixedPoint FPGA Based Hardware Design. / P.
Banerjee, D. Bagchi, M. Haldar et al. // FCCM.IEEE Computer Society, 2003.P. 263–264.URL: "http://dblp.uni-trier.de/db/conf/fccm/fccm2003.html#BanerjeeBHNKU03".17445. Sung W., Kum K.-I. Simulation-based word-length optimization method forfixed-point digital signal processing systems. // IEEE Transactions on SignalProcessing. 1995. Vol. 43, no. 12. P. 3087–3090. URL: "http://dblp.uni-trier.de/db/journals/tsp/tsp43.html#SungK95".46.
Smart bit-width allocation for low power optimization in a systemc based ASICdesign environment. / A. Mallik, D. Sinha, P. Banerjee et al. // DATE / Ed.by G. G. E. Gielen. European Design and Automation Association, Leuven,Belgium, 2006. P. 618–623. URL: "http://dblp.uni-trier.de/db/conf/date/date2006p.html#MallikSBZ06".47.
Han K., of Texas at Austin T. U. Automating Transformations from Floatingpoint to Fixed-point for Implementing Digital Signal Processing Algorithms.University of Texas at Austin, 2006. URL: "http://books.google.ru/books?id=VW0htwAACAAJ".48. Hai Nam N., Ménard D., Sentieys O. Novel Algorithms for Word-lengthOptimization // 19th European Signal Processing Conference (EUSIPCO2011).Barcelona, Spain: 2011.