11ETD (1086184), страница 3
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10-3Result Registers .............................................................................. 10-3A/D Converter Clocks ...................................................................... 10-4Conversion Sequence ..................................................................... 10-4A/D Converter Power-Up and Clock Select ............................................. 10-4Conversion Process ................................................................................ 10-5Channel Assignments .............................................................................
10-6Single-Channel Operation ....................................................................... 10-6Multiple-Channel Operation ..................................................................... 10-6Operation in STOP and WAIT Modes ..................................................... 10-7A/D Control/Status Registers .................................................................. 10-7A/D Converter Result Registers ..............................................................
10-8APPENDIX A ELECTRICAL CHARACTERISTICSAPPENDIX B MECHANICAL DATA AND ORDERING INFORMATIONB.1B.2Ordering Information ................................................................................ B-1Obtaining M68HC11 E-Series Mechanical Information ............................ B-4APPENDIX CDEVELOPMENT SUPPORTC.1Motorola M68HC11 E-Series Development Tools ................................... C-1M68HC11 E SERIESTECHNICAL DATAMOTOROLAviiTABLE OF CONTENTSParagraphC.2C.3C.4(Continued)TitlePageEVS — Evaluation System .......................................................................
C-1Motorola Modular Development System (MMDS11) ................................ C-1SPGMR11— Serial Programmer for M68HC11 MCUs ............................ C-3SUMMARY OF CHANGESMOTOROLAviiiM68HC11 E SERIESTECHNICAL DATALIST OF ILLUSTRATIONSFigure1-12-12-22-32-42-52-62-72-82-92-103-13-24-14-24-34-44-55-15-15-25-25-37-17-27-37-47-58-18-29-19-29-310-110-210-3A-1A-2A-3A-4A-5A-6TitlePageM68HC11 E-Series Block Diagram ................................................................ 1-2Pin Assignments for 52-Pin PLCC and CLCC ................................................ 2-1Pin Assignments for 64-Pin QFP ....................................................................
2-2Pin Assignments for 52-Pin Thin QFP ............................................................ 2-3Pin Assignments for 56-Pin SDIP ................................................................... 2-4Pin Assignments for 48-Pin DIP (MC68HC811E2) ........................................
2-5External Reset Circuit ..................................................................................... 2-6External Reset Circuit with Delay ................................................................... 2-6Common Crystal Connections ........................................................................ 2-7External Oscillator Connections ..................................................................... 2-7One Crystal Driving Two MCUs ..................................................................... 2-8Programming Model .......................................................................................
3-1Stacking Operations ....................................................................................... 3-3Address/Data Demultiplexing ......................................................................... 4-2Memory Map for MC68HC11E0, MC68HC11E1, MC68HC11E8, andMC68HC(7)11E9 ............................................................................................ 4-3Memory Map for MC68HC(7)11E20 ............................................................... 4-4Memory Map for MC68HC811E2 ................................................................... 4-5RAM Standby MODB/VSTBY Connections .................................................... 4-9Processing Flow out of Reset (1 of 2) ..........................................................
5-12Processing Flow out of Reset (2 of 2) .......................................................... 5-13Interrupt Priority Resolution (1 of 2) ............................................................. 5-14Interrupt PriorityResolution (2 of 2) .............................................................. 5-15Interrupt Source Resolution Within SCI ........................................................
5-16SCI Transmitter Block Diagram ...................................................................... 7-2SCI Receiver Block Diagram .......................................................................... 7-4SCI Baud Rate Generator Block Diagram .................................................... 7-11MC68HC(7)11E20 SCI Baud Rate Generator Block Diagram ..................... 7-12Interrupt Source Resolution Within SCI ........................................................ 7-14SPI Block Diagram .........................................................................................
8-2SPI Transfer Format ....................................................................................... 8-3Timer Clock Divider Chains ............................................................................ 9-2Capture/Compare Block Diagram .................................................................. 9-4Pulse Accumulator ....................................................................................... 9-16A/D Converter Block Diagram ...................................................................... 10-2Electrical Model of an A/D Input Pin (Sample Mode) ...................................
10-3A/D Conversion Sequence ........................................................................... 10-4Test Methods .................................................................................................. A-4Timer Inputs ...................................................................................................
A-6POR External Reset Timing Diagram ............................................................. A-7STOP Recovery Timing Diagram ................................................................... A-8WAIT Recovery from Interrupt Timing Diagram ............................................. A-9Interrupt Timing Diagram .............................................................................. A-10M68HC11 E SERIESTECHNICAL DATAMOTOROLAixLIST OF ILLUSTRATIONS(Continued)TitleFigureA-7A-8A-9A-10A-11A-12A-13A-14A-15A-15PagePort Read Timing Diagram ...........................................................................
A-12Port Write Timing Diagram ........................................................................... A-13Simple Input Strobe Timing Diagram ........................................................... A-13Simple Output Strobe Timing Diagram ......................................................... A-13Port C Input Handshake Timing Diagram ..................................................... A-14Port C Output Handshake Timing Diagram .................................................. A-14Three-State Variation of Output Handshake Timing Diagram(STRA Enables Output Buffer) .....................................................................
A-15Multiplexed Expansion Bus Timing Diagram ................................................ A-20SPI Timing Diagram (1 of 2) ......................................................................... A-23SPI Timing Diagram (2 of 2) ......................................................................... A-24MOTOROLAxM68HC11 E SERIESTECHNICAL DATALIST OF TABLESTable2-13-13-24-14-24-34-44-54-64-74-84-95-15-25-35-45-56-16-27-17-28-19-19-29-39-49-59-69-710-110-2A-1A-2A-3A-3aA-4A-4aA-5A-5aA-6A-6aA-7A-7aTitlePagePort Signal Functions .................................................................................... 2-10Reset Vector Comparison ............................................................................... 3-4Instruction Set .................................................................................................
3-8Register and Control Bit Assignments............................................................. 4-6Hardware Mode Select Summary ................................................................. 4-10Write Access Limited Registers..................................................................... 4-12EEPROM Mapping ........................................................................................ 4-13RAM Mapping................................................................................................ 4-15Register Mapping ..........................................................................................
4-15EEPROM Block Protect................................................................................. 4-21EEPROM Block Protect (MC68HC811E2) .................................................... 4-21EEPROM Erase ............................................................................................ 4-22COP Timer Rate Select................................................................................... 5-2Reset Cause, Reset Vector, and Operating Mode ..........................................
5-4Highest Priority Interrupt Selection.................................................................. 5-8Interrupt and Reset Vector Assignments......................................................... 5-9Stacking Order on Entry to Interrupts............................................................ 5-10Input/Output Ports ........................................................................................... 6-1Parallel I/O Control .......................................................................................... 6-6Baud Rate Prescaler Selects ........................................................................
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