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The X interrupt mask bit is set only by hardware (RESETor XIRQ acknowledge). X is cleared only by program instruction (TAP, where the associated bit of A is zero; or RTI, where bit 6 of the value loaded into the CCR from thestack has been cleared). There is no hardware action for clearing X.M68HC11 E SERIESTECHNICAL DATACENTRAL PROCESSING UNITMOTOROLA3-533.1.6.8 Stop Disable (S)Setting the STOP disable (S) bit prevents the STOP instruction from putting theM68HC11 into a low-power stop condition. If the STOP instruction is encountered bythe CPU while the S bit is set, it is treated as a no-operation (NOP) instruction, andprocessing continues to the next instruction. S is set by reset — STOP disabled by default.3.2 Data TypesThe M68HC11 CPU supports the following data types:3• Bit data• 8-bit and 16-bit signed and unsigned integers• 16-bit unsigned fractions• 16-bit addressesA byte is eight bits wide and can be accessed at any byte location.
A word is composedof two consecutive bytes with the most significant byte at the lower value address. Because the M68HC11 is an 8-bit CPU, there are no special requirements for alignmentof instructions or operands.3.3 Opcodes and OperandsThe M68HC11 Family of microcontrollers uses 8-bit opcodes. Each opcode identifiesa particular instruction and associated addressing mode to the CPU. Several opcodesare required to provide each instruction with a range of addressing capabilities. Only256 opcodes would be available if the range of values were restricted to the numberable to be expressed in 8-bit binary numbers.A four-page opcode map has been implemented to expand the number of instructions.An additional byte, called a prebyte, directs the processor from page 0 of the opcodemap to one of the other three pages. As its name implies, the additional byte precedesthe opcode.A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, orthree operands.
The operands contain information the CPU needs for executing theinstruction. Complete instructions can be from one to five bytes long.3.4 Addressing ModesSix addressing modes can be used to access memory: immediate, direct, extended,indexed, inherent, and relative. These modes are detailed in the following paragraphs.All modes except inherent mode use an effective address.
The effective address is thememory address from which the argument is fetched or stored, or the address fromwhich execution is to proceed. The effective address can be specified within an instruction, or it can be calculated.3.4.1 ImmediateIn the immediate addressing mode an argument is contained in the byte(s) immediately following the opcode. The number of bytes following the opcode matches the sizeMOTOROLA3-6CENTRAL PROCESSING UNITM68HC11 E SERIESTECHNICAL DATAof the register or memory location being operated on.
There are two-, three-, and four(if prebyte is required) byte immediate instructions. The effective address is the address of the byte following the instruction.3.4.2 DirectIn the direct addressing mode, the low-order byte of the operand address is containedin a single byte following the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00 – $FF are thus accessed directly, using two-byte instructions. Execution time is reduced by eliminating the additional memory accessrequired for the high-order address byte. In most applications, this 256- byte area isreserved for frequently referenced data.
In M68HC11 MCUs, the memory map can beconfigured for combinations of internal registers, RAM, or external memory to occupythese addresses.3.4.3 ExtendedIn the extended addressing mode, the effective address of the argument is containedin two bytes following the opcode byte. These are three-byte instructions (or four-byteinstructions if a prebyte is required). One or two bytes are needed for the opcode andtwo for the effective address.3.4.4 IndexedIn the indexed addressing mode, an 8-bit unsigned offset contained in the instructionis added to the value contained in an index register (IX or IY). The sum is the effectiveaddress. This addressing mode allows referencing any memory location in the 64Kbyte address space.
These are two- to five-byte instructions, depending on whetheror not a prebyte is required.3.4.5 InherentIn the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations that use only the index registers or accumulators, as well as control instructions with no arguments, are included in thisaddressing mode. These are one- or two-byte instructions.3.4.6 RelativeThe relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit signed offset included in the instruction is added to the contentsof the program counter to form the effective branch address. Otherwise, control proceeds to the next instruction. These are usually two-byte instructions.3.5 Instruction SetRefer to Table 3-2, which shows all the M68HC11 instructions in all possible addressing modes.
For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E-clock cycles.M68HC11 E SERIESTECHNICAL DATACENTRAL PROCESSING UNITMOTOROLA3-73Table 3-2 Instruction Set (Sheet 1 of 6)MnemonicABAABXABYADCA (opr)3OperationAddAccumulatorsAdd B to XAdd B to YAdd with Carryto ADescriptionAddressingModeINHA+B⇒AIX + (00 : B) ⇒ IXIY + (00 : B) ⇒ IYA+M+C⇒AADCB (opr)Add with Carryto BB+M+C⇒BADDA (opr)Add Memoryto AA+M⇒AADDB (opr)Add Memoryto BB+M⇒BADDD (opr)Add 16-Bit to D D + (M : M + 1) ⇒ DANDA (opr)AND A withMemoryA•M⇒AANDB (opr)AND B withMemoryB•M⇒BASL (opr)ArithmeticShift LeftCASLA0b01818181818181818183A3A8999B9A9A9C9D9F9E9E98B9BBBABABCBDBFBEBEBC3D3F3E3E38494B4A4A4C4D4F4E4E4786868——iiddhh llffffiiddhh llffffiiddhh llffffiiddhh llffffjj kkddhh llffffiiddhh llffffiiddhh llffffhh llffff3423445234452344523445456672344523445667S—X—Condition CodesHINZ∆—∆∆V∆C∆————————∆—————∆——∆——∆——∆——∆—∆∆∆∆——∆—∆∆∆∆——∆—∆∆∆∆————∆∆∆∆————∆∆0—————∆∆0—————∆∆∆∆AINH48—2————∆∆∆∆BINH58—2————∆∆∆∆INH05—3————∆∆∆∆77676747hh llffff—6672————∆∆∆∆AEXTIND,XIND,YINH————∆∆∆∆BINH57—2————∆∆∆∆REL24rr3————————151D1D25dd mmff mmff mmrr6783————∆∆0—?C=1DIRIND,XIND,YREL————————?Z=1REL27rr3————————?N⊕V=0REL2Crr3————————b70b0ArithmeticShift Left BCASLDb7AAAAABBBBBArithmeticShift Left ACASLBAAAAABBBBBAAAAABBBBBINHINHIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YEXTIND,XIND,YInstructionOpcodeOperand Cycles1B—2b70b0ArithmeticShift Left D0C b7 A b0 b7 B b0ASRArithmeticShift RightASRAArithmeticShift Right AASRBArithmeticShift Right BBCC (rel)Branch if CarryClearClear Bit(s)b7b7b7BCLR (opr)(msk)BCS (rel)BEQ (rel)BGE (rel)Branch if CarrySetBranch if =ZeroBranch if ∆ZeroMOTOROLA3-8b0b0b0C18CC?C=0M • (mm) ⇒ M18CENTRAL PROCESSING UNITM68HC11 E SERIESTECHNICAL DATATable 3-2 Instruction Set (Sheet 2 of 6)MnemonicBGT (rel)BHI (rel)BHS (rel)BITA (opr)BITB (opr)OperationBranch if >ZeroBranch ifHigherBranch ifHigher orSameBit(s) Test Awith Memory? Z + (N ⊕ V) = 0Bit(s) Test Bwith MemoryB•MBranch if ∆ZeroBLO (rel)Branch ifLowerBLS (rel)Branch ifLower orSameBLT (rel)Branch if <ZeroBMI (rel)Branch ifMinusBNE (rel)Branch if not =ZeroBPL (rel)Branch if PlusBRA (rel)Branch AlwaysBRCLR(opr)Branch if(msk)Bit(s) Clear(rel)BRN (rel)Branch NeverBRSET(opr)Branch if Bit(s)(msk)Set(rel)BSET (opr)Set Bit(s)(msk)BLE (rel)BSR (rel)BVC (rel)BVS (rel)CBACLCCLICLR (opr)CLRACLRBCLVCMPA (opr)CMPB (opr)DescriptionS—X—Condition CodesHINZ————V—C—REL22rr3————————?C=0REL24rr3————————IMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YREL8595B5A5A5C5D5F5E5E52Fiiddhh llffffiiddhh llffffrr23445234453————∆∆0—————∆∆0—————————A•MAAAAABBBBB? Z + (N ⊕ V) = 11818?C=1REL25rr3————————?C+Z=1REL23rr3————————?N⊕V=1REL2Drr3————————?N=1REL2Brr3————————?Z=0REL26rr3————————RELRELDIRIND,XIND,YRELDIRIND,XIND,YDIRIND,XIND,YREL2A20131F1F21121E1E141C1C8Drrrrdd mm rrff mm rrff mm rrrrdd mm rrff mm rrff mm rrdd mmff mmff mmrr3367836786786————————————————————————————————————————————∆∆0—————————?N=0?1=1? M • mm = 0?1=0? (M) • mm = 0M + mm ⇒ MSee Figure 3–2ClearAccumulator AClearAccumulator BClear OverflowFlagCompare A toMemory0⇒A0⇒BM68HC11 E SERIESTECHNICAL DATAInstructionOpcodeOperand Cycles2E rr3?C+Z=0Branch toSubroutineBranch ifOverflow ClearBranch ifOverflow SetCompare A toBClear Carry BitClear InterruptMaskClear MemoryByteCompare B toMemoryAddressingModeREL181818?V=0REL28rr3————————?V=1REL29rr3————————A–BINH11—2————∆∆∆∆0⇒C0⇒IINHINH0C0E——22———————0——————0—0⇒M7F6F6F4Fhh llffff—6672————0100AEXTIND,XIND,YINH————0100BINH5F—2————0100INH0A—2——————0—IMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,Y8191B1A1A1C1D1F1E1E12344523445————∆∆∆∆————∆∆∆∆0⇒VA–MB–MAAAAABBBBB181818iiddhh llffffiiddhh llffffCENTRAL PROCESSING UNITMOTOROLA3-93Table 3-2 Instruction Set (Sheet 3 of 6)MnemonicCOM (opr)COMACOMBCPD (opr)3OperationOnesComplementMemory ByteOnesComplementAOnesComplementBCompare D toMemory 16-BitDescription$FF – A ⇒ AAddressingModeEXTIND,XIND,YAINH$FF – B ⇒ BB$FF – M ⇒ MD–M:M +1InstructionOpcodeOperand Cycles73 hh ll663 ff61863 ff743—2INHIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YINHX—Condition CodesHINZ——∆∆————∆V0C1∆01—2————∆∆018393B3A3A38C9CBCACAC8C9CBCACAC19jj kkddhh llffffjj kkddhh llffffjj kkddhh llffff—5677745667567772————∆∆∆∆————∆∆∆∆————∆∆∆∆————∆∆∆∆7A6A6A4Ahh llffff—6672————∆∆∆—————∆∆∆—531A1A1A1ACDS—CPX (opr)Compare X toMemory 16-BitIX – M : M + 1CPY (opr)Compare Y toMemory 16-BitIY – M : M + 1DAADecimal AdjustADecrementMemory ByteAdjust Sum to BCDDecrementAccumulatorADecrementAccumulatorBDecrementStack PointerDecrementIndex RegisterXDecrementIndex RegisterYExclusive ORA with MemoryA–1⇒AAEXTIND,XIND,YINHB–1⇒BBINH5A—2————∆∆∆—SP – 1 ⇒ SPINH34—3————————IX – 1 ⇒ IXINH09—3—————∆——IY – 1 ⇒ IYINH09—4—————∆——iiddhh llffffiiddhh llffff—234452344541————∆∆0—————∆∆0——————∆∆∆DEC (opr)DECADECBDESDEXDEYEORA (opr)M–1⇒MA⊕M⇒A1818EORB (opr)Exclusive ORB with MemoryB⊕M⇒BFDIVFractionalDivide 16 by16Integer Divide16 by 16IncrementMemory ByteD / IX ⇒ IX; r ⇒ DIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YINHD / IX ⇒ IX; r ⇒ DINH02—41—————∆0∆7C6C6C4Chh llffff—6672————∆∆∆—————∆∆∆—IDIVINC (opr)INCAINCBINSINXIncrementAccumulatorAIncrementAccumulatorBIncrementStack PointerIncrementIndex RegisterXMOTOROLA3-10AAAAABBBBBCD1818181A18M+1⇒M18188898B8A8A8C8D8F8E8E803A+1⇒AAEXTIND,XIND,YINHB+1⇒BBINH5C—2————∆∆∆—SP + 1 ⇒ SPINH31—3————————IX + 1 ⇒ IXINH08—3—————∆——18CENTRAL PROCESSING UNITM68HC11 E SERIESTECHNICAL DATATable 3-2 Instruction Set (Sheet 4 of 6)MnemonicINYJMP (opr)OperationDescriptionAddressingModeINHIY + 1 ⇒ IYIncrementIndex RegisterYJumpSee Figure 3–2JSR (opr)Jump toSubroutineSee Figure 3–2LDAA (opr)LoadAccumulatorAM⇒ALDAB (opr)LoadAccumulatorBM⇒BLDD (opr)Load DoubleAccumulatorDM ⇒ A,M + 1 ⇒ BLDS (opr)Load StackPointerM : M + 1 ⇒ SPLoad IndexRegisterXM : M + 1 ⇒ IXLDY (opr)Load IndexRegisterYM : M + 1 ⇒ IYLSL (opr)Logical ShiftLeftCLSLACLSLBLSRALSRBLSRDMULNEG (opr)NEGANEGBb7b0b7b0Logical ShiftRightLogical ShiftRight A0Logical ShiftRight BLogical ShiftRight DoubleMultiply 8 by 8Two’sComplementMemory ByteTwo’sComplementATwo’sComplementBM68HC11 E SERIESTECHNICAL DATA00b7b7b7Condition CodesHINZ———∆V—C—————————————————————∆∆0—————∆∆0—————∆∆0—————∆∆0—————∆∆0—————∆∆0—ABINH58—2————∆∆∆∆INH05—3————∆∆∆∆74646444hh llffff—6672————0∆∆∆AEXTIND,XIND,YINH————0∆∆∆BINH54—2————0∆∆∆INH04—3————0∆∆∆3D70606040—hh llffff—106672—————————∆—∆—∆∆∆————∆∆∆∆50—2————∆∆∆∆1818181818CD1818181A1818hh llffffddhh llffffiiddhh llffffiiddhh llffffjj kkddhh llffffjj kkddhh llffffjj kkddhh llffffjj kkddhh llffffhh llffff—33456672344523445345563455634556456666672————∆∆∆∆————∆∆∆∆0b7 A b0 b7 B b00X—0Logical ShiftLeft DoubleCLSR (opr)b0Logical ShiftLeft BCLSLDb7Logical ShiftLeft A0187E6E6E9DBDADAD8696B6A6A6C6D6F6E6E6CCDCFCECEC8E9EBEAEAECEDEFEEEEECEDEFEEEEE78686848S—EXTIND,XIND,YDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YEXTIND,XIND,YINHAAAAABBBBBLDX (opr)InstructionOpcodeOperand Cycles1808—40b0 C18b0 Cb0 Cb7 A b0 b7 B b0 CA∗B⇒D0–M⇒M0–A⇒AAINHEXTIND,XIND,YINH0–B⇒BBINH18CENTRAL PROCESSING UNITMOTOROLA3-113Table 3-2 Instruction Set (Sheet 5 of 6)MnemonicNOPORAA (opr)ORAB (opr)PSHAPSHBPSHXPSHYPULA3PULBPULXPULYROL (opr)OperationNo operationORAccumulatorA (Inclusive)DescriptionNo OperationA+M⇒AAAAAAORB+M⇒BBAccumulatorBB (Inclusive)BBBPush A onto A ⇒ Stk,SP = SP – 1 AStackPush B onto B ⇒ Stk,SP = SP – 1 BStackPush X onto IX ⇒ Stk,SP = SP – 2Stack (LoFirst)Push Y onto IY ⇒ Stk,SP = SP – 2Stack (LoFirst)Pull A from SP = SP + 1, A ⇐ Stk AStackPull B from SP = SP + 1, B ⇐ Stk BStackPull X FromSP = SP + 2, IX ⇐Stack (HiStkFirst)Pull Y fromSP = SP + 2, IY ⇐Stack (HiStkFirst)Rotate Left———∆————C——∆0—————INH37—3————————INH3C—4————————3C—5————————INH32—4————————INH33—4————————INH38—5————————1838—6————————hh llffff—6672————∆∆∆∆1879696949————∆∆∆∆INHINH18—2————∆∆∆∆76666646hh llffff—6672————∆∆∆∆AEXTIND,XIND,YINH————∆∆∆∆BINH56—2————∆∆∆∆See Figure 3–2INH3B—12∆↓∆∆∆∆∆∆See Figure 3–2INH39—5————————A–B⇒AINH10—2————∆∆∆∆8292B2A2A2C2D2F2E2E20D0Fiiddhh llffffiiddhh llffff——234452344522————∆∆∆∆————∆∆∆∆1⇒C1⇒IIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YINHINH———————1——————1—1⇒VINH0B—2——————1—DIREXTIND,XIND,Y97B7A7A73445————∆∆0—ROR (opr)Rotate RightRORARotate Right ARORBRotate Right BRTIReturn fromInterruptReturn fromSubroutineSubtract Bfrom ASubtract withCarry from ASBCB (opr)Subtract withCarry from BB–M–C⇒BSECSEISet CarrySet InterruptMaskSet OverflowFlagStoreAccumulatorACb7b7b7MOTOROLA3-12—V—059CSTAA (opr)Condition CodesHINZ——————∆∆INHb0Rotate Left BSEVX——Bb7ROLBSBCA (opr)S——ACRotate Left ASBAInstructionOpcodeOperand Cycles01—28A ii29A dd3BA hh ll4AA ff418AA ff5CA ii2DA dd3FA hh ll4EA ff418EA ff536—3EXTIND,XIND,YINHROLARTSAddressingModeINHIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YINHb7b0b0b7b0 C18b0 Cb0 CA–M–C⇒AA⇒MAAAAABBBBBAAAA181818ddhh llffffCENTRAL PROCESSING UNITM68HC11 E SERIESTECHNICAL DATATable 3-2 Instruction Set (Sheet 6 of 6)MnemonicOperationDescriptionSTAB (opr)StoreAccumulatorBB⇒MSTD (opr)StoreAccumulatorDA ⇒ M, B ⇒ M + 1STOPStop InternalClocksStore StackPointer—STS (opr)SP ⇒ M : M + 1STX (opr)Store IndexRegister XIX ⇒ M : M + 1STY (opr)Store IndexRegister YIY ⇒ M : M + 1SUBA (opr)SubtractMemory fromAA–M⇒ASUBB (opr)SubtractMemory fromBB–M⇒BSUBD (opr)SubtractMemory fromDD–M:M+1⇒DSWITABTAPTBATESTTPATST (opr)TSTATSTBTSXTSYTXSTYSWAIXGDXXGDYBBBBAAAAAAAAAASoftwareSee Figure 3–2InterruptTransfer A to BA⇒BTransfer A toA ⇒ CCRCC RegisterTransfer B to AB⇒ATEST (Only in Address Bus CountsTest Modes)Transfer CCCCR ⇒ ARegister to ATest for ZeroM–0or MinusTest A for ZeroA–0Aor MinusTest B for ZeroB–0Bor MinusTransferSP + 1 ⇒ IXStack Pointerto XTransferSP + 1 ⇒ IYStack Pointerto YTransfer X toIX – 1 ⇒ SPStack PointerTransfer Y toIY – 1 ⇒ SPStack PointerWait forStack Regs & WAITInterruptExchange DIX ⇒ D, D ⇒ IXwith XExchange DIY ⇒ D, D ⇒ IYwith YM68HC11 E SERIESTECHNICAL DATAAddressingModeDIREXTIND,XIND,YDIREXTIND,XIND,YINHDIREXTIND,XIND,YDIREXTIND,XIND,YDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YIMMDIREXTIND,XIND,YINHInstructionOpcodeOperand CyclesD7 dd3F7 hh ll4E7 ff418E7 ff5DD dd4FD hh ll5ED ff518ED ff6CF—218CD18181A181818189FBFAFAFDFFFEFEFDFFFEFEF8090B0A0A0C0D0F0E0E08393B3A3A33FS—X—Condition CodesHINZ——∆∆————∆————V0C—∆0—————ddhh llffffddhh llffffddhh llffffiiddhh llffffiiddhh llffffjj kkddhh llffff—45564556566623445234454566714————∆∆0—————∆∆0—————∆∆0—————∆∆∆∆————∆∆∆∆————∆∆∆∆———1————INHINH1606——22—∆—↓—∆—∆∆∆∆∆0∆—∆INHINH1700——2*————————∆—∆—0———INH07—2————————EXTIND,XIND,YINH7D6D6D4Dhh llffff—6672————∆∆00————∆∆00INH5D—2————∆∆00INH30—3————————30—4————————35—3————————35—4————————INH3E—**————————INH8F—3————————8F—4————————INH1818INHINHINH1818CENTRAL PROCESSING UNITMOTOROLA3-133Cycle***Infinity or until reset occurs12 Cycles are used beginning with the opcode fetch.
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