Интерфейсный документ GPS (1014597), страница 7
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When the X2A is in the last state of its 3750th cycle and X2B is in thelast state of its 3749th cycle, their transitions to their respective initial states are delayed by 37 chip time durations.At the beginning of the GPS week, X1A, X1B, X2A and X2B shift registers are initialized to produce the first chipof the week. The precession of the shift registers with respect to X1A continues until the last X1A period of theGPS week interval. During this particular X1A period, X1B, X2A and X2B are held when reaching the last stateof their respective cycles until that X1A cycle is completed (see Table 3-VI). At this point, all four shift registersare initialized and provide the first chip of the new week.Figure 3-6 shows a functional P-code mechanization. Signal component timing is shown in Figure 3-7, while theend-of-week reset timing and the final code vector states are given in Tables 3-VI and 3-VII, respectively.IS-GPS-200D7 Dec 20042510.23 MHzCRX1AREGISTER1612IX1EPOCHSET X1A EPOCHA4092DECODE6, 8, 11, 123750RESUMECLOCKCONTROLHALTZ-COUNTER403,200CI1SET X1BEPOCHRX1BREGISTER3749B127 DAYRESET4093DECODE1, 2, 5, 8,9, 10, 11, 12REGISTERINPUTSEND/WEEKCLOCKCONTROLHALTC - CLOCKI - INPUTR - RESET TOINITIALCONDITIONSON NEXTCLOCK3750CI1SET X2AEPOCHRX2AREGISTERC124092DECODE1, 3, 4, 5, 7,8, 9, 10, 11, 12START/WEEKRESUMEX2EPOCH37ENABLEAX1END/WEEKHALTPiBCLOCKCONTROLCIX2BREGISTER1 212RX2 iSET X2BEPOCH3749C4093DECODE2, 3, 4,8, 9, 12X21iSHIFTREGISTERFigure 3-6.
P-Code GenerationIS-GPS-200D7 Dec 200426012301230X1 EPOCHS37 Chips74 ChipsX2 EPOCHS *P EpochTIME01.5 sec3.0 sec4.5 sec7 days14 days* Does not include any offset due to PRN delay.Figure 3-7. P-Code Signal Component TimingIS-GPS-200D7 Dec 200427Table 3-VI.P-Code Reset Timing(Last 400 µsec of 7-day period) **Code ChipX1A-CodeX1B-CodeX2A-CodeX2B-Code13451070967••••••••••••3023336740923989••••••••••••3127347140924093••••••••••••3749409340924093••••••••••••4093409240934092** Last Chip of Week.** Does not include any X2 offset due to PRN delay.IS-GPS-200D7 Dec 200428Table 3-VII.CodeX1AX1BX2AX2BFinal Code Vector StatesChip NumberVector State40911000100100104092000100100100409210010101010140930010101010104091111001001001409211001001001040920001010101014093001010101010Vector State for 1st Chipfollowing Epoch001001001000010101010100100100100101010101010100NOTE: First Chip in each sequence is output bit whose leading edge occurs simultaneously with the epoch.IS-GPS-200D7 Dec 2004293.3.2.3 C/A-Code Generation.
Each Gi(t) sequence is a 1023-bit Gold-code which is itself the modulo-2 sum of two1023-bit linear patterns, G1 and G2i. The G2i sequence is formed by effectively delaying the G2 sequence by aninteger number of chips. The G1 and G2 sequences are generated by 10-stage shift registers having the followingpolynomials as referred to in the shift register input (see Figures 3-8 and 3-9).G1 = X10 + X3 + 1, andG2 = X10 + X9 + X8 + X6 + X3 + X2 + 1.The initialization vector for the G1 and G2 sequences is 1111111111.
The G1 and G2 shift registers are initializedat the P-coder X1 epoch. The G1 and G2 registers are clocked at 1.023 MHz derived from the 10.23 MHz P-coderclock. The initialization by the X1 epoch phases the 1.023 MHz clock to insure that the first chip of the C/A codebegins at the same time as the first chip of the P-code.The effective delay of the G2 sequence to form the G2i sequence may be accomplished by combining the output oftwo stages of the G2 shift register by modulo-2 addition (see Figure 3-10).However, this two-tap coderimplementation generates only a limited set of valid C/A codes.
Table 3-I contains a tabulation of the G2 shiftregister taps selected and their corresponding P-code X2i and PRN signal numbers together with the first severalchips of each resultant PRN code. Timing relationships related to the C/A code are shown in Figure 3-11.IS-GPS-200D7 Dec 200430POLYNOMIAL G1:1 + X 3 + X 10STAGENUMBERSINPUT012345678910111111111112345678INITIALCONDITIONS9OUTPUT10TAPNUMBERSSHIFT DIRECTIONFigure 3-8. G1 Shift Register Generator ConfigurationIS-GPS-200D7 Dec 200431POLYNOMIAL G2:1 + X 2 + X 3 +X 6 + X 8 + X 9 + X 10STAGENUMBERSINPUT012345678910111111111112345678INITIALCONDITIONS9OUTPUT10TAPNUMBERSSHIFT DIRECTIONFigure 3-9.G2 Shift Register Generator ConfigurationIS-GPS-200D7 Dec 200432310X1 EPOCHISC10.23 MHzSYNCH102G EPOCH1 Kbps3ICSSYNCH20G1G1REGISTER68910G2REGISTER1023DECODEGiG2iPHASE SELECTLOGIC50 bps TO DATA ENCODERREGISTER INPUTSCIS-CLOCKINPUTSET ALL ONESFigure 3-10.
Example C/A-Code GenerationIS-GPS-200D7 Dec 200433X1 Epoch @ 2/3 bps102310231023102310231023 BIT Gold Code @ 1023 Kbps01etc.1 msec218190Gold Code Epochs @ 1000/secData @ 50 cps20 msecFigure 3-11. C/A-Code Timing RelationshipsIS-GPS-200D7 Dec 2004343.3.2.4 L2 CM-/L2 CL-Code Generation. Each CM,i(t) pattern (L2 CM-code) and CL,i(t) pattern (L2 CL-code) aregenerated using the same code generator polynomial each clocked at 511.5 Kbps. Each pattern is initiated andreset with a specified initial state (defined in Table 3-II). CM,i(t) pattern is reset after 10230 chips resulting in acode period of 20 milliseconds, and CL,i(t) pattern is reset after 767250 chips resulting in a code period of 1.5seconds.
The L2 CM and L2 CL shift registers are initialized at the P-coder X1 epoch. The first L2 CM-codechip starts synchronously with the end/start of week epoch. Timing relationships related to the L2 CM-/L2 CLcodes are shown in Figure 3-12.The maximal polynomial used for L2 CM- and L2 CL-codes is 1112225171 (octal) of degree 27.
The L2 CM andL2 CL code generator is conceptually described in Figure 3-13 using modular-type shift register generator.IS-GPS-200D7 Dec 20043501End/start of week1.5 secondX1 Epoch @ 2/3 bpsetc.767250 Chips767250 BIT L2 CL-Code @ 511.5 Kbps1102302102303102304731023010230741023010230 BIT L2 CM-Code @ 511.5 Kbps7510230etc.20 msecData @ 50 cpsL2 CM @ 511.5 KbpsL2 CL @ 511.5 KbpsL2 C @ 1023 KbpsFigure 3-12.L2 CM-/L2 CL-Code Timing RelationshipsIS-GPS-200D7 Dec 200436Figure 3-13.L2 CM/L2 CL Shift Register Generator ConfigurationIS-GPS-200D7 Dec 20043732332345691123SHIFT DIRECTION11 + X + X +X + X + X + X + XINITIAL CONDITIONS ARE A FUNCTION OF PRN AND CODE PERIOD (MODERATE/LONG)3DELAYNUMBERSPOLYNOMIAL:13161+X19+X121+X24327+X +XOUTPUT3.3.3 Navigation Data.
The content and format of the NAV data, D(t), and the CNAV data, DC(t), are given inAppendices II and III, respectively, of this document.3.3.3.1 Navigation Data Modulation (L2 CM). For Block IIR-M, Block IIF, and subsequent blocks of SVs, theCNAV bit train, DC(t), is rate ½ encoded and, thus, clocked at 50 sps.
The resultant symbol sequence is thenmodulo-2 added to the L2 CM-code. During the initial period of Block IIR-M SVs operation, prior to InitialOperational Capability of L2 C signal, and upon ground command, the NAV bit train, D(t), at one of two data rates,may be modulo-2 added to the L2 CM-code instead of CNAV data, DC(t), as further described in Section 3.2.2.3.3.3.1.1 Forward Error Correction. The CNAV bit train, DC(t), will always be Forward Error Correction (FEC)encoded by a rate 1/2 convolutional code. For Block IIR-M, the NAV bit train, D(t), can be selected to beconvolutionally encoded.
The resulting symbol rate is 50 sps. The convolutional coding will be constraint length 7,with a convolutional encoder logic arrangement as illustrated in Figure 3-14. The G1 symbol is selected on theoutput as the first half of a 40-millisecond data bit period.Twelve-second navigation messages broadcast by the SV are synchronized with every eighth of the SV's P(Y)-codeX1 epochs. However, the navigation message is FEC encoded in a continuous process independent of messageboundaries (i.e. at the beginning of each new message, the encoder registers illustrated in Figure 3-14 contains thelast six bits of the previous message).Because the FEC encoding convolves successive messages, it is necessary to define which transmitted symbol issynchronized to SV time, as follows. The beginning of the first symbol that contains any information about the firstbit of a message will be synchronized to every eighth X1 epoch (referenced to end/start of week).
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