Интерфейсный документ GPS (1014597), страница 6
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The crosstalk is the relative power level of the undesired signal to the desired reference signal.3.3.1.6 User-Received Signal Levels. The SV shall provide L1 and L2 navigation signal strength at end-of-life(EOL), worst-case, in order to meet the minimum levels specified in Table 3-V. The minimum received power ismeasured at the output of a 3 dBi linearly polarized user receiving antenna (located near ground) at worst normalorientation, when the SV is above a 5-degree elevation angle. The received signal levels are observed within the inband allocation defined in para. 3.3.1.1.The Block IIF SV shall provide L1 and L2 signals with the following characteristic: the L1 off-axis power gainshall not decrease by more than 2 dB from the Edge-of-Earth (EOE) to nadir, nor more than 10 dB from EOE to 20degrees off nadir, and no more than 18 dB from EOE to 23 degrees off nadir; the L2 off-axis power gain shall notdecrease by more than 2 dB from EOE to nadir, and no more than 10 dB from EOE to 23 degrees off nadir; thepower drop off between EOE and ±23 degrees shall be in a monotonically decreasing fashion.Additional related data is provided as supporting material in paragraph 6.3.1.IS-GPS-200D7 Dec 200415Table 3-IV.
Composite L1 Transmitted Signal Phase ** (Block II/IIA and IIR SVs Only)Nominal Composite L1Signal Phase*0°-70.5°+109.5°180°***Code StatePC/A01010011Relative to 0, 0 code state with positive angles leading and negative angles lagging.Based on the composite of two L1 carrier components with 3 dB difference in the power levels of the two.Table 3-V.SV BlocksReceived Minimum RF Signal StrengthSignalChannelP(Y)C/A or L2 CL1-161.5 dBW-158.5 dBWL2-164.5 dBWL1-161.5 dBW-158.5 dBWL2-161.5 dBW-160.0 dBWII/IIA/IIRor-164.5 dBWIIR-M/IIFIS-GPS-200D7 Dec 2004163.3.1.7 Equipment Group Delay.
Equipment group delay is defined as the delay between the signal radiated outputof a specific SV (measured at the antenna phase center) and the output of that SV's on-board frequency source; thedelay consists of a bias term and an uncertainty. The bias term is of no concern to the US since it is included in theclock correction parameters relayed in the NAV data, and is therefore accounted for by the user computations ofsystem time (reference paragraphs 20.3.3.3.3.1, 30.3.3.2.3). The uncertainty (variation) of this delay as well as thegroup delay differential between the signals of L1 and L2 are defined in the following.3.3.1.7.1 Group Delay Uncertainty.
The effective uncertainty of the group delay shall not exceed 3.0 nanoseconds(two sigma).3.3.1.7.2 Group Delay Differential. The group delay differential between the radiated L1 and L2 signals (i.e. L1P(Y) and L2 P(Y), L1 P(Y) and L2 C) is specified as consisting of random plus bias components. The meandifferential is defined as the bias component and will be either positive or negative. For a given navigation payloadredundancy configuration, the absolute value of the mean differential delay shall not exceed 15.0 nanoseconds.The random variations about the mean shall not exceed 3.0 nanoseconds (two sigma).
Corrections for the biascomponents of the group delay differential are provided to the US in the Nav message using parameters designatedas TGD (reference paragraph 20.3.3.3.3.2) and Inter-Signal Correction (ISC) (reference paragraph 30.3.3.3.1.1).3.3.1.8 Signal Coherence. All transmitted signals for a particular SV shall be coherently derived from the sameon-board frequency standard; all digital signals shall be clocked in coincidence with the PRN transitions for the Psignal and occur at the P-signal transition speed. On the L1 channel the data transitions of the two modulatingsignals (i.e., that containing the P(Y)-code and that containing the C/A-code), L1 P(Y) and L1 C/A, shall be suchthat the average time difference between the transitions does not exceed 10 nanoseconds (two sigma).3.3.1.9 Signal Polarization.
The transmitted signal shall be right-hand circularly polarized (RHCP). For theangular range of ±14.3 degrees from boresight, L1 ellipticity shall be no worse than 1.2 dB for Block II/IIA andshall be no worse than 1.8 dB for Block IIR/IIR-M/IIF SVs. L2 ellipticity shall be no worse than 3.2 dB for BlockII/IIA SVs and shall be no worse than 2.2 dB for Block IIR/IIR-M/IIF over the angular range of ±14.3 degrees fromboresight.IS-GPS-200D7 Dec 2004173.3.2 PRN Code Characteristics. The characteristics of the P-, L2 CM-, L2 CL-, and the C/A-codes are definedbelow in terms of their structure and the basic method used for generating them. Figure 3-1 depicts a simplifiedblock diagram of the scheme for generating the 10.23 Mbps Pi(t) and the 1.023 Mbps Gi(t) patterns (referred to as Pand C/A-codes respectively), and for modulo-2 summing these patterns with the NAV bit train, D(t), which isclocked at 50 bps.
The resultant composite bit trains are then used to modulate the signal carriers.3.3.2.1 Code Structure. The Pi(t) pattern (P-code) is generated by the modulo-2 summation of two PRN codes,X1(t) and X2(t - iT), where T is the period of one P-code chip and equals (1.023 x 107)-1 seconds, while i is aninteger from 1 through 37. This allows the generation of 37 unique P(t) code phases (identified in Table 3-I) usingthe same basic code generator.The linear Gi(t) pattern (C/A-code) is the modulo-2 sum of two 1023-bit linear patterns, G1 and G2i. The lattersequence is selectively delayed by an integer number of chips to produce many different G(t) patterns (defined inTable 3-I).The CM,i(t) pattern (L2 CM-code) is a linear pattern which is reset with a specified initial state every code count of10230 chips.
Different initial states are used to generate different CM,i(t) patterns (defined in Table 3-II).The CL,i(t) pattern (L2 CL-code) is also a linear pattern but with a longer reset period of 767250 chips. Differentinitial states are used to generate different CL,i(t) patterns (defined in Table 3-II).For a given SV-ID, two different initial states are used to generate different CL,i(t) and CM,i(t) patterns.IS-GPS-200D7 Dec 200418EPOCHDETECTX1 EPOCHEPOCHRESET20Z-COUNT50 Hz1 KHzX1 CODEGENERATORZCOUNTER101.023MHzGOLD CODEGENERATORX1(t)EPOCHDETECTGi(t)RESETCOMMANDGENERATORGi(t)RECLOCKINGDEVICED(t)FORMATTEDDATAX2i(t)Pi(t)REMOTECOMMANDCODESELECTDEVICED(t)Pi(t)EPOCHRESETX2 CODEGENERATORFigure 3-1.10.23 MHzFREQUENCYSOURCEDATAENCODERD(t)Pi(t)Generation of P-, C/A-Codes and Modulating SignalsIS-GPS-200D7 Dec 2004193.3.2.2 P-Code Generation.
Each Pi(t) pattern is the modulo-2 sum of two extended patterns clocked at 10.23 Mbps(X1 and X2i). X1 itself is generated by the modulo-2 sum of the output of two 12-stage registers (X1A and X1B)short cycled to 4092 and 4093 chips respectively. When the X1A short cycles are counted to 3750, the X1 epoch isgenerated. The X1 epoch occurs every 1.5 seconds after 15,345,000 chips of the X1 pattern have been generated.The polynomials for X1A and X1B, as referenced to the shift register input, are:X1A: 1 + X6 + X8 + X11 + X12, andX1B: 1 + X1 + X2 + X5 + X8 + X9 + X10 + X11 + X12.Samples of the relationship between shift register taps and the exponents of the corresponding polynomial,referenced to the shift register input, are as shown in Figures 3-2, 3-3, 3-4 and 3-5.The state of each generator can be expressed as a code vector word which specifies the binary sequence constant ofeach register as follows: (a) the vector consists of the binary state of each stage of the register, (b) the stage 12value appears at the left followed by the values of the remaining states in order of descending stage numbers, and(c) the shift direction is from lower to higher stage number with stage 12 providing the current output.
This codevector convention represents the present output and 11 future outputs in sequence. Using this convention, at eachX1 epoch, the X1A shift register is initialized to code vector 001001001000 and the X1B shift register is initializedto code vector 010101010100. The first chip of the X1A sequence and the first chip of the X1B sequence occursimultaneously in the first chip interval of any X1 period.The natural 4095 chip cycles of these generating sequences are shortened to cause precession of the X1B sequencewith respect to the X1A sequence during subsequent cycles of the X1A sequence in the X1 period.Re-initialization of the X1A shift register produces a 4092 chip sequence by omitting the last 3 chips (001) of thenatural 4095 chip X1A sequence.
Re-initialization of the X1B shift register produces a 4093 chip sequence byomitting the last 2 chips (01) of the natural 4095 chip X1B sequence. This results in the phase of the X1Bsequence lagging by one chip for each X1A cycle in the X1 period.The X1 period is defined as the 3750 X1A cycles (15,345,000 chips) which is not an integer number of X1Bcycles. To accommodate this situation, the X1B shift register is held in the final state (chip 4093) of its 3749thcycle. It remains in this state until the X1A shift register completes its 3750th cycle (343 additional chips). Thecompletion of the 3750th X1A cycle establishes the next X1 epoch which re-initializes both the X1A and X1B shiftregisters starting a new X1 cycle.IS-GPS-200D7 Dec 200420POLYNOMIAL X1A:1 + X 6 + X 8 + X 11 + X 12STAGENUMBERS01234567891011120001001001001234567INITIALCONDITIONS891011OUTPUT12TAPNUMBERSSHIFT DIRECTIONFigure 3-2.X1A Shift Register Generator ConfigurationIS-GPS-200D7 Dec 200421POLYNOMIAL X1B:125891210111+X +X +X +X +X +X +X +XSTAGENUMBERS01234567891011120010101010101234567INITIALCONDITIONS891011OUTPUT12TAPNUMBERSSHIFT DIRECTIONFigure 3-3.
X1B Shift Register Generator ConfigurationIS-GPS-200D7 Dec 200422POLYNOMIAL X2A:13457891011121+X +X +X +X +X +X +X +X +X +XSTAGENUMBERS01234567891011121010010010011234567INITIALCONDITIONS891011OUTPUT12TAPNUMBERSSHIFT DIRECTIONFigure 3-4. X2A Shift Register Generator ConfigurationIS-GPS-200D7 Dec 200423POLYNOMIAL X2B:34892121+X +X +X +X +X +XSTAGENUMBERS01234567891011120010101010101234567INITIALCONDITIONS891011OUTPUT12TAPNUMBERSSHIFT DIRECTIONFigure 3-5. X2B Shift Register Generator ConfigurationIS-GPS-200D7 Dec 200424The X2i sequences are generated by first producing an X2 sequence and then delaying it by a selected integernumber of chips, i, ranging from 1 to 37. Each of the X2i sequences is then modulo-2 added to the X1 sequencethereby producing up to 37 unique P(t) sequences.The X2A and X2B shift registers, used to generate X2, operate in a similar manner to the X1A and X1B shiftregisters.
They are short-cycled, X2A to 4092 and X2B to 4093, so that they have the same relative precession rateas the X1 shift registers. X2A epochs are counted to include 3750 cycles and X2B is held in the last state at 3749cycle until X2A completes its 3750th cycle. The polynomials for X2A and X2B, as referenced to the shift registerinput, are:X2A: 1 + X1 + X3 + X4 + X5 + X7 + X8 + X9 + X10 + X11 + X12, andX2B: 1 + X2 + X3 + X4 + X8 + X9 + X12.(The initialization vector for X2A is 100100100101 and for X2B is 010101010100).The X2A and X2B epochs are made to precess with respect to the X1A and X1B epochs by causing the X2 periodto be 37 chips longer than the X1 period.
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