ATmega128 (961843), страница 23
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Reading theOCRnA/B/C 16-bit registers does not involve using the Temporary Register.To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read,the low byte must be read before the high byte.The following code examples show how to access the 16-bit timer registers assumingthat no interrupts updates the temporary register. The same principle can be useddirectly for accessing the OCRnA/B/C and ICRn Registers. Note that when using “C”,the compiler handles the 16-bit access.Assembly Code Examples(1)...; Set TCNTn to 0x01FFldi r17,0x01ldi r16,0xFFout TCNTnH,r17out TCNTnL,r16; Read TCNTn into r17:r16in r16,TCNTnLin r17,TCNTnH...C Code Examples(1)unsigned int i;.../* Set TCNTn to 0x01FF */TCNTn = 0x1FF;/* Read TCNTn into i */i = TCNTn;...Note:1.
The example code assumes that the part specific header file is included.For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and“SBI” instructions must be replaced with instructions that allow access to extendedI/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.The assembly code example returns the TCNTn value in the r17:r16 register pair.112ATmega1282467M–AVR–11/04ATmega128It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interruptcode updates the temporary register by accessing the same or any other of the 16-bitTimer Registers, then the result of the access outside the interrupt will be corrupted.Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access.The following code examples show how to do an atomic read of the TCNTn Registercontents.
Reading any of the OCRnA/B/C or ICRn Registers can be done by using thesame principle.Assembly Code Example(1)TIM16_ReadTCNTn:; Save global interrupt flagin r18,SREG; Disable interruptscli; Read TCNTn into r17:r16in r16,TCNTnLin r17,TCNTnH; Restore global interrupt flagout SREG,r18retC Code Example(1)unsigned int TIM16_ReadTCNTn( void ){unsigned char sreg;unsigned int i;/* Save global interrupt flag */sreg = SREG;/* Disable interrupts */__disable_interrupt();/* Read TCNTn into i */i = TCNTn;/* Restore global interrupt flag */SREG = sreg;return i;}Note:1.
The example code assumes that the part specific header file is included.For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and“SBI” instructions must be replaced with instructions that allow access to extendedI/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.The assembly code example returns the TCNTn value in the r17:r16 register pair.1132467M–AVR–11/04The following code examples show how to do an atomic write of the TCNTn Registercontents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using thesame principle.Assembly Code Example(1)TIM16_WriteTCNTn:; Save global interrupt flagin r18,SREG; Disable interruptscli; Set TCNTn to r17:r16out TCNTnH,r17out TCNTnL,r16; Restore global interrupt flagout SREG,r18retC Code Example(1)void TIM16_WriteTCNTn( unsigned int i ){unsigned char sreg;unsigned int i;/* Save global interrupt flag */sreg = SREG;/* Disable interrupts */__disable_interrupt();/* Set TCNTn to i */TCNTn = i;/* Restore global interrupt flag */SREG = sreg;}Note:1.
The example code assumes that the part specific header file is included.For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and“SBI” instructions must be replaced with instructions that allow access to extendedI/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.The assembly code example requires that the r17:r16 register pair contains the value tobe written to TCNTn.Reusing the Temporary HighByte Register114If writing to more than one 16-bit register where the high byte is the same for all registerswritten, then the high byte only needs to be written once.
However, note that the samerule of atomic operation described previously also applies in this case.ATmega1282467M–AVR–11/04ATmega128Timer/Counter ClockSourcesThe Timer/Counter can be clocked by an internal or an external clock source. The clocksource is selected by the clock select logic which is controlled by the Clock Select(CSn2:0) bits located in the Timer/Counter Control Register B (TCCRnB). For details onc l oc k s ou r c e s a n d p re s c al er , s e e “ T i m e r/ C o u nt e r3 , Ti me r /C ou n te r 2, a n dTimer/Counter1 Prescalers” on page 142.Counter UnitThe main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directionalcounter unit.
Figure 47 shows a block diagram of the counter and its surroundings.Figure 47. Counter Unit Block DiagramDATA BUS (8-bit)TOVn(Int.Req.)TEMP (8-bit)Clock SelectCountTCNTnH (8-bit) TCNTnL (8-bit)TCNTn (16-bit Counter)ClearDirectionControl LogicclkTnEdgeDetectorTn( From Prescaler )TOPBOTTOMSignal description (internal signals):CountIncrement or decrement TCNTn by 1.DirectionSelect between increment and decrement.ClearClear TCNTn (set all bits to zero).clkTnTimer/Counter clock.TOPSignalize that TCNTn has reached maximum value.BOTTOMSignalize that TCNTn has reached minimum value (zero).The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High(TCNTnH) containing the upper 8 bits of the counter, and Counter Low (TCNTnL) containing the lower 8 bits.
The TCNTnH Register can only be indirectly accessed by theCPU. When the CPU does an access to the TCNTnH I/O location, the CPU accessesthe high byte Temporary Register (TEMP). The Temporary Register is updated with theTCNTnH value when the TCNTnL is read, and TCNTnH is updated with the TemporaryRegister value when TCNTnL is written. This allows the CPU to read or write the entire16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to noticethat there are special cases of writing to the TCNTn Register when the counter is counting that will give unpredictable results. The special cases are described in the sectionswhere they are of importance.Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each Timer Clock (clkTn). The clkTn can be generated from an external orinternal clock source, selected by the Clock Select bits (CSn2:0). When no clock sourceis selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can beaccessed by the CPU, independent of whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations.The counting sequence is determined by the setting of the Waveform Generation modebits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and1152467M–AVR–11/04TCCRnB).
There are close connections between how the counter behaves (counts) andhow waveforms are generated on the output compare outputs OCnx. For more detailsabout advanced counting sequences and waveform generation, see “Modes of Operation” on page 121.The Timer/Counter Overflow (TOVn) flag is set according to the mode of operationselected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.Input Capture UnitThe Timer/Counter incorporates an Input Capture unit that can capture external eventsand give them a time-stamp indicating time of occurrence.
The external signal indicatingan event, or multiple events, can be applied via the ICPn pin or alternatively, for theTimer/Counter1 only, via the Analog Comparator unit. The time-stamps can then beused to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.The Input Capture unit is illustrated by the block diagram shown in Figure 48.
The elements of the block diagram that are not directly a part of the Input Capture unit are grayshaded. The small “n” in register and bit names indicates the Timer/Counter number.Figure 48. Input Capture Unit Block DiagramDATA BUS(8-bit)TEMP (8-bit)ICRnH (8-bit)WRITEICRnL (8-bit)TCNTnH (8-bit)ICRn (16-bit Register)ACO*AnalogComparatorACIC*TCNTnL (8-bit)TCNTn (16-bit Counter)ICNCICESNoiseCancelerEdgeDetectorICFn (Int.Req.)ICPnNote:The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – notTimer/Counter3.When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn),alternatively on the analog Comparator output (ACO), and this change confirms to thesetting of the edge detector, a capture will be triggered.
When a capture is triggered, the16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). TheInput Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copiedinto ICRn Register. If enabled (TICIEn = 1), the Input Capture flag generates an InputCapture interrupt. The ICFn flag is automatically cleared when the interrupt is executed.Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/Obit location.116ATmega1282467M–AVR–11/04ATmega128Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading thelow byte (ICRnL) and then the high byte (ICRnH).
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