ATmega128 (961843), страница 18
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CPU accessibleI/O registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/Oregister and bit locations are listed in the “8-bit Timer/Counter Register Description” onpage 101.Figure 34. 8-bit Timer/Counter Block DiagramTCCRncountTOVn(Int.Req.)clearControl LogicdirectionclkTnTOSC1BOTTOMTOPPrescalerT/COscillatorTOSC2Timer/CounterTCNTn=0= 0xFFOCn(Int.Req.)WaveformGeneration=clk I/OOCnDATABUSOCRnSynchronized Status flagsclk I/OSynchronization Unitclk ASYStatus flagsASSRnasynchronous modeselect (ASn)RegistersThe Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers.Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt FlagRegister (TIFR).
All interrupts are individually masked with the Timer Interrupt MaskRegister (TIMSK). TIFR and TIMSK are not shown in the figure since these registers areshared by other timer units.The Timer/Counter can be clocked internally, via the prescaler, or asynchronouslyclocked from the TOSC1/2 pins, as detailed later in this section.
The asynchronous90ATmega1282467M–AVR–11/04ATmega128operation is controlled by the Asynchronous Status Register (ASSR). The Clock Selectlogic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. Theoutput from the clock select logic is referred to as the timer clock (clkT0).The double buffered Output Compare Register (OCR0) is compared with theTimer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output ComparePin (OC0). See “Output Compare Unit” on page 92.
for details. The compare matchevent will also set the compare flag (OCF0) which can be used to generate an outputcompare interrupt request.DefinitionsMany register and bit references in this document are written in general form. A lowercase “n” replaces the Timer/Counter number, in this case 0. However, when using theregister or bit defines in a program, the precise form must be used (i.e., TCNT0 foraccessing Timer/Counter0 counter value and so on).The definitions in Table 51 are also used extensively throughout the document.Table 51. DefinitionsBOTTOMThe counter reaches the BOTTOM when it becomes zero (0x00).MAXThe counter reaches its MAXimum when it becomes 0xFF (decimal 255).TOPThe counter reaches the TOP when it becomes equal to the highestvalue in the count sequence. The TOP value can be assigned to be thefixed value 0xFF (MAX) or the value stored in the OCR0 Register.
Theassignment is dependent on the mode of operation.Timer/Counter ClockSourcesThe Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT0 is by default equal to the MCU clock, clkI/O.When the AS0 bit in the ASSR Register is written to logic one, the clock source is takenfrom the Timer/Counter Oscillator connected to TOSC1 and TOSC2.
For details onasynchronous operation, see “Asynchronous Status Register – ASSR” on page 104. Fordetails on clock sources and prescaler, see “Timer/Counter Prescaler” on page 107.Counter UnitThe main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.Figure 35 shows a block diagram of the counter and its surrounding environment.Figure 35. Counter Unit Block DiagramDATA BUSTOVn(Int.Req.)TOSC1countTCNTnclearclk TnControl LogicPrescalerT/COscillatordirectionbottomTOSC2topclkI/O912467M–AVR–11/04Signal description (internal signals):countIncrement or decrement TCNT0 by 1.directionSelects between increment and decrement.clearClear TCNT0 (set all bits to zero).clkT0Timer/Counter clock.topSignalizes that TCNT0 has reached maximum value.bottomSignalizes that TCNT0 has reached minimum value (zero).Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
clkT0 can be generated from an external or internalclock source, selected by the clock select bits (CS02:0). When no clock source isselected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessedby the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (haspriority over) all counter clear or count operations.The counting sequence is determined by the setting of the WGM01 and WGM00 bitslocated in the Timer/Counter Control Register (TCCR0).
There are close connectionsbetween how the counter behaves (counts) and how waveforms are generated on theoutput compare output OC0. For more details about advanced counting sequences andwaveform generation, see “Modes of Operation” on page 95.The Timer/Counter overflow (TOV0) flag is set according to the mode of operationselected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.Output Compare Unit92The 8-bit comparator continuously compares TCNT0 with the Output Compare Register(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match.
A match willset the output compare flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1),the output compare flag generates an output compare interrupt. The OCF0 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0 flag can becleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by theWGM01:0 bits and compare output mode (COM01:0) bits.
The max and bottom signalsare used by the waveform generator for handling the special cases of the extreme values in some modes of operation (“Modes of Operation” on page 95). Figure 36 shows ablock diagram of the output compare unit.ATmega1282467M–AVR–11/04ATmega128Figure 36. Output Compare Unit, Block DiagramDATA BUSOCRnTCNTn= (8-bit Comparator )OCFn (Int.Req.)topbottomWaveform GeneratorOCxyFOCnWGMn1:0COMn1:0The OCR0 Register is double buffered when using any of the Pulse Width Modulation(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,the double buffering is disabled. The double buffering synchronizes the update of theOCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, therebymaking the output glitch-free.The OCR0 Register access may seem complex, but this is not case.
When the doublebuffering is enabled, the CPU has access to the OCR0 buffer Register, and if doublebuffering is disabled the CPU will access the OCR0 directly.Force Output CompareIn non-PWM waveform generation modes, the match output of the comparator can beforced by writing a one to the Force Output Compare (FOC0) bit. Forcing comparematch will not set the OCF0 flag or reload/clear the timer, but the OC0 pin will beupdated as if a real compare match had occurred (the COM01:0 bits settings definewhether the OC0 pin is set, cleared or toggled).Compare Match Blocking byTCNT0 WriteAll CPU write operations to the TCNT0 Register will block any compare match thatoccurs in the next timer clock cycle, even when the timer is stopped.
This feature allowsOCR0 to be initialized to the same value as TCNT0 without triggering an interrupt whenthe Timer/Counter clock is enabled.Using the Output CompareUnitSince writing TCNT0 in any mode of operation will block all compare matches for onetimer clock cycle, there are risks involved when changing TCNT0 when using the outputcompare channel, independently of whether the Timer/Counter is running or not. If thevalue written to TCNT0 equals the OCR0 value, the compare match will be missed,resulting in incorrect waveform generation. Similarly, do not write the TCNT0 valueequal to BOTTOM when the counter is downcounting.932467M–AVR–11/04The setup of the OC0 should be performed before setting the Data Direction Register forthe port pin to output.
The easiest way of setting the OC0 value is to use the force outputcompare (FOC0) strobe bit in normal mode. The OC0 Register keeps its value evenwhen changing between waveform generation modes.Be aware that the COM01:0 bits are not double buffered together with the comparevalue. Changing the COM01:0 bits will take effect immediately.Compare Match OutputUnitThe Compare Output mode (COM01:0) bits have two functions.
The waveform generator uses the COM01:0 bits for defining the Output Compare (OC0) state at the nextcompare match. Also, the COM01:0 bits control the OC0 pin output source. Figure 37shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/Oregisters, I/O bits, and I/O pins in the figure are shown in bold.
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