ATmega128 (961843), страница 16
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The OC3C pin is also the output pin for thePWM mode timer function.• INT4/OC3B – Port E, Bit 4INT4, External Interrupt source 4: The PE4 pin can serve as an External Interruptsource.OC3B, Output Compare Match B output: The PE4 pin can serve as an External outputfor the Timer/Counter3 Output Compare B. The pin has to be configured as an output(DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWMmode timer function.• AIN1/OC3A – Port E, Bit 3AIN1 – Analog Comparator Negative input. This pin is directly connected to the negativeinput of the Analog Comparator.78ATmega1282467M–AVR–11/04ATmega128OC3A, Output Compare Match A output: The PE3 pin can serve as an External outputfor the Timer/Counter3 Output Compare A.
The pin has to be configured as an output(DDE3 set “one”) to serve this function. The OC3A pin is also the output pin for the PWMmode timer function.• AIN0/XCK0 – Port E, Bit 2AIN0 – Analog Comparator Positive input. This pin is directly connected to the positiveinput of the Analog Comparator.XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whetherthe clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active onlywhen the USART0 operates in Synchronous mode.• PDO/TXD0 – Port E, Bit 1PDO, SPI Serial Programming Data Output.
During Serial Program Downloading, thispin is used as data output line for the ATmega128.TXD0, UART0 Transmit pin.• PDI/RXD0 – Port E, Bit 0PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pinis used as data input line for the ATmega128.RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When theUSART0 receiver is enabled this pin is configured as an input regardless of the value ofDDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 willturn on the internal pull-up.Table 40 and Table 41 relates the alternate functions of Port E to the overriding signalsshown in Figure 33 on page 68.Table 40.
Overriding Signals for Alternate Functions PE7..PE4SignalNamePE7/INT7/ICP3PE6/INT6/T3PE5/INT5/OC3CPE4/INT4/OC3BPUOE0000PUOV0000DDOE0000DDOV0000PVOE00OC3C ENABLEOC3B ENABLEPVOV00OC3COC3BDIEOEINT7 ENABLEINT6 ENABLEINT5 ENABLEINT4 ENABLEDIEOV1111DIINT7 INPUT/ICP3INPUTINT7 INPUT/T3INPUTINT5 INPUTINT4 INPUTAIO––––792467M–AVR–11/04Table 41. Overriding Signals for Alternate Functions in PE3..PE0Alternate Functions of Port FSignal NamePE3/AIN1/OC3APE2/AIN0/XCK0PE1/PDO/TXD0PE0/PDI/RXD0PUOE00TXEN0RXEN0PUOV000PORTE0 • PUDDDOE00TXEN0RXEN0DDOV0010PVOEOC3B ENABLEUMSEL0TXEN00PVOVOC3BXCK0 OUTPUTTXD00DIEOE0000DIEOV0000DI0XCK0 INPUT–RXD0AIOAIN1 INPUTAIN0 INPUT––The Port F has an alternate function as analog input for the ADC as shown in Table 42.If some Port F pins are configured as outputs, it is essential that these do not switchwhen a conversion is in progress.
This might corrupt the result of the conversion. InATmega103 compatibility mode Port F is input only. If the JTAG interface is enabled, thepull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if aReset occurs.Table 42. Port F Pins Alternate FunctionsPort PinAlternate FunctionPF7ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)PF6ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)PF5ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select)PF4ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)PF3ADC3 (ADC input channel 3)PF2ADC2 (ADC input channel 2)PF1ADC1 (ADC input channel 1)PF0ADC0 (ADC input channel 0)• TDI, ADC7 – Port F, Bit 7ADC7, Analog to Digital Converter, Channel 7.TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register orData Register (scan chains).
When the JTAG interface is enabled, this pin can not beused as an I/O pin.• TDO, ADC6 – Port F, Bit 6ADC6, Analog to Digital Converter, Channel 6.TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin.The TDO pin is tri-stated unless TAP states that shift out data are entered.• TMS, ADC5 – Port F, Bit 580ATmega1282467M–AVR–11/04ATmega128ADC5, Analog to Digital Converter, Channel 5.TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controllerstate machine. When the JTAG interface is enabled, this pin can not be used as an I/Opin.• TCK, ADC4 – Port F, Bit 4ADC4, Analog to Digital Converter, Channel 4.TCK, JTAG Test Clock: JTAG operation is synchronous to TCK.
When the JTAG interface is enabled, this pin can not be used as an I/O pin.• ADC3 – ADC0 – Port F, Bit 3..0Analog to Digital Converter, Channel 3..0.Table 43. Overriding Signals for Alternate Functions in PF7..PF4SignalNamePF7/ADC7/TDIPF6/ADC6/TDOPF5/ADC5/TMSPF4/ADC4/TCKPUOEJTAGENJTAGENJTAGENJTAGENPUOV1011DDOEJTAGENJTAGENJTAGENJTAGENDDOV0SHIFT_IR +SHIFT_DR00PVOE0JTAGEN00PVOV0TDO00DIEOEJTAGENJTAGENJTAGENJTAGENDIEOV0000DI––––AIOTDI/ADC7 INPUTADC6 INPUTTMS/ADC5INPUTTCKADC4 INPUTTable 44. Overriding Signals for Alternate Functions in PF3..PF0Signal NamePF3/ADC3PF2/ADC2PF1/ADC1PF0/ADC0PUOE0000PUOV0000DDOE0000DDOV0000PVOE0000PVOV0000DIEOE0000DIEOV0000DI––––AIOADC3 INPUTADC2 INPUTADC1 INPUTADC0 INPUT812467M–AVR–11/04Alternate Functions of Port GIn ATmega103 compatibility mode, only the alternate functions are the defaults for PortG, and Port G cannot be used as General Digital Port Pins.
The alternate pin configuration is as follows:Table 45. Port G Pins Alternate FunctionsPort PinAlternate FunctionPG4TOSC1 (RTC Oscillator Timer/Counter0)PG3TOSC2 (RTC Oscillator Timer/Counter0)PG2ALE (Address Latch Enable to external memory)PG1RD (Read strobe to external memory)PG0WR (Write strobe to external memory)• TOSC1 – Port G, Bit 4TOSC2, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG4 is disconnected from the port, andbecomes the input of the inverting Oscillator amplifier. In this mode, a Crystal Oscillatoris connected to this pin, and the pin can not be used as an I/O pin.• TOSC2 – Port G, Bit 3TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG3 is disconnected from the port, andbecomes the inverting output of the Oscillator amplifier.
In this mode, a Crystal Oscillatoris connected to this pin, and the pin can not be used as an I/O pin.• ALE – Port G, Bit 2ALE is the external data memory Address Latch Enable signal.• RD – Port G, Bit 1RD is the external data memory read control strobe.• WR – Port G, Bit 0WR is the external data memory write control strobe.Table 46 and Table 47 relates the alternate functions of Port G to the overriding signalsshown in Figure 33 on page 68.Table 46.
Overriding Signals for Alternate Functions in PG4..PG182Signal NamePG4/TOSC1PG3/TOSC2PG2/ALEPG1/RDPUOEAS0AS0SRESREPUOV0000DDOEAS0AS0SRESREDDOV0011PVOE00SRESREPVOV00ALERDDIEOEAS0AS000DIEOV0000DI––––AIOT/C0 OSC INPUTT/C0 OSC OUTPUT––ATmega1282467M–AVR–11/04ATmega128Table 47. Overriding Signals for Alternate Functions in PG0Signal NamePG0/WRPUOESREPUOV0DDOESREDDOV1PVOESREPVOVWRDIEOE0DIEOV0DI–AIO–832467M–AVR–11/04Register Description forI/O PortsPort A Data Register – PORTABitPort A Data Direction Register– DDRAPort A Input Pins Address –PINA76543210PORTA7PORTA6PORTA5PORTA4PORTA3PORTA2PORTA1PORTA0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210DDA7DDA6DDA5DDA4DDA3DDA2DDA1DDA0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit7PINA7Read/WriteRInitial ValueN/A6543210PINA6PINA5PINA4PINA3PINA2PINA1PINA0RRRRRRRN/AN/AN/AN/AN/AN/AN/APORTADDRAPINAPort B Data Register – PORTBBitPort B Data Direction Register– DDRBPort B Input Pins Address –PINB76543210PORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210DDB7DDB6DDB5DDB4DDB3DDB2DDB1DDB0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210PINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB0Read/WriteRRRRRRRRInitial ValueN/AN/AN/AN/AN/AN/AN/AN/APORTBDDRBPINBPort C Data Register – PORTCBitPort C Data Direction Register– DDRC8476543210PORTC7PORTC6PORTC5PORTC4PORTC3PORTC2PORTC1PORTC0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210DDC7DDC6DDC5DDC4DDC3DDC2DDC1DDC0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000PORTCDDRCATmega1282467M–AVR–11/04ATmega128Port C Input Pins Address –PINCBit76543210PINC7PINC6PINC5PINC4PINC3PINC2PINC1PINC0Read/WriteRRRRRRRRInitial ValueN/AN/AN/AN/AN/AN/AN/AN/APINCIn ATmega103 compatibility mode, DDRC and PINC Registers are initialized to beingPush-Pull Zero Output.
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