ATmega128 (961732), страница 61
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Parallel Programming Characteristics, VCC = 5 V ± 10% (Continued)SymbolParametertBVDVBS1 Valid to DATA validtOLDVtOHDZNotes:MinMaxUnits250nsOE Low to DATA Valid250nsOE High to DATA Tri-stated250ns0Typ1.tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lockbits commands.2. tWLRH_CE is valid for the Chip Erase command.Serial DownloadingBoth the Flash and EEPROM memory arrays can be programmed using the serial SPIbus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI(input) and MISO (output). After RESET is set low, the Programming Enable instructionneeds to be executed first before program/erase operations can be executed. NOTE, inTable 127 on page 303, the pin mapping for SPI programming is listed.
Not all parts usethe SPI pins dedicated for the internal SPI interface. Note that throughout the description about Serial downloading, MOSI and MISO are used to describe the serial data inand serial data out respectively. For ATmega128 these pins are mapped to PDI andPDO.SPI Serial ProgrammingPin MappingEven though the SPI Programming interface re-uses the SPI I/O module, there is oneimportant difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPII/O module are not used in the Programming interface.
Instead, PE0 and PE1 are usedfor data in SPI Programming mode as shown in Table 127.Table 127. Pin Mapping SPI Serial ProgrammingSymbolPinsI/ODescriptionMOSI (PDI)PE0ISerial data inMISO (PDO)PE1OSerial data outSCKPB1ISerial clock3032467M–AVR–11/04Figure 144. SPI Serial Programming and Verify(1)+2.7 - 5.5VVCC+2.7 - 5.5V(2)PDIPE0PDOPE1SCKPB1AVCCXTAL1RESETGNDNotes:1.
If the device is clocked by the Internal Oscillator, it is no need to connect a clocksource to the XTAL1 pin.2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 2.7 - 5.5V.When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to first execute theChip Erase instruction. The Chip Erase operation turns the content of every memorylocation in both the Program and EEPROM arrays into $FF.Depending on CKSEL Fuses, a valid clock must be present. The minimum low and highperiods for the serial clock (SCK) input are defined as follows:Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHzHigh:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHzSPI Serial ProgrammingAlgorithmWhen writing serial data to the ATmega128, data is clocked on the rising edge of SCK.When reading data from the ATmega128, data is clocked on the falling edge of SCK.See Figure 145 for timing details.To program and verify the ATmega128 in the SPI Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 145):1.
Power-up sequence:Apply power between VCC and GND while RESET and SCK are set to “0”. Insome systems, the programmer can not guarantee that SCK is held low duringpower-up. In this case, RESET must be given a positive pulse of at least twoCPU clock cycles duration after SCK has been set to “0”.As an alternative to using the RESET signal, PEN can be held low during Poweron Reset while SCK is set to “0”. In this case, only the PEN value at Power-onReset is important. If the programmer cannot guarantee that SCK is held lowduring power-up, the PEN method cannot be used. The device must be powereddown in order to commence normal operation when using this method.2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming Enable serial instruction to pin MOSI.304ATmega1282467M–AVR–11/04ATmega1283.
The SPI Serial Programming instructions will not work if the communication isout of synchronization. When in sync. the second byte ($53), will echo backwhen issuing the third byte of the Programming Enable instruction. Whether theecho is correct or not, all FOUR bytes of the instruction must be transmitted.
Ifthe $53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.4. The Flash is programmed one page at a time. The page size is found in Table124 on page 293. The memory page is loaded one byte at a time by supplyingthe 7 LSB of the address and data together with the Load Program MemoryPage instruction. To ensure correct loading of the page, the data low byte mustbe loaded before data high byte is applied for given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction withthe 9 MSB of the address.
If polling is not used, the user must wait at leasttWD_FLASH before issuing the next page. (See Table 128).Note: If other commands than polling (read) are applied before any write operation(Flash, EEPROM, Lock bits, Fuses) is completed, may result in incorrectprogramming.5. The EEPROM array is programmed one byte at a time by supplying the addressand data together with the appropriate Write instruction.
An EEPROM memorylocation is first automatically erased before new data is written. If polling is notused, the user must wait at least tWD_EEPROM before issuing the next byte. (SeeTable 128). In a chip erased device, no $FFs in the data file(s) need to beprogrammed.6. Any memory location can be verified by using the Read instruction which returnsthe content at the selected address at serial output MISO.7.
At the end of the programming session, RESET can be set high to commencenormal operation.8. Power-off sequence (if needed):Set RESET to “1”.Turn VCC power off.Data Polling FlashWhen a page is being programmed into the Flash, reading an address location withinthe page being programmed will give the value $FF. At the time the device is ready for anew page, the programmed value will read correctly. This is used to determine when thenext page can be written. Note that the entire page is written simultaneously and anyaddress within the page can be used for polling.
Data polling of the Flash will not workfor the value $FF, so when programming this value, the user will have to wait for at leasttWD_FLASH before programming the next page. As a chip-erased device contains $FF inall locations, programming of addresses that are meant to contain $FF, can be skipped.See Table 128 for tWD_FLASH valueData Polling EEPROMWhen a new byte has been written and is being programmed into EEPROM, reading theaddress location being programmed will give the value $FF.
At the time the device isready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, but the usershould have the following in mind: As a chip-erased device contains $FF in all locations,programming of addresses that are meant to contain $FF, can be skipped. This doesnot apply if the EEPROM is re-programmed without chip-erasing the device. In thiscase, data polling cannot be used for the value $FF, and the user will have to wait atleast tWD_EEPROM before programming the next byte. See Table 128 for tWD_EEPROMvalue.3052467M–AVR–11/04Table 128. Minimum Wait Delay before Writing the Next Flash or EEPROM Location,VCC = 5 V ± 10%SymbolMinimum Wait DelaytWD_FUSE4.5 mstWD_FLASH5 mstWD_EEPROM10 mstWD_ERASE10 msFigure 145. .SPI Serial Programming WaveformsSERIAL DATA INPUT(MOSI)MSBLSBSERIAL DATA OUTPUT(MISO)MSBLSBSERIAL CLOCK INPUT(SCK)SAMPLE306ATmega1282467M–AVR–11/04ATmega128Table 129.
SPI Serial Programming Instruction SetInstruction FormatInstructionByte 1Byte 2Byte 3Byte4Programming Enable1010 11000101 0011xxxx xxxxxxxx xxxxEnable SPI Serial Programming after RESETgoes low.Chip Erase1010 1100100x xxxxxxxx xxxxxxxx xxxxChip Erase EEPROM and Flash.Read ProgramMemory0010 H000aaaa aaaabbbb bbbboooo ooooLoad ProgramMemory Page0100 H000xxxx xxxxxbbb bbbbiiii iiiiWrite ProgramMemory Page0100 1100aaaa aaaabxxx xxxxxxxx xxxxRead EEPROMMemory1010 0000xxxx aaaabbbb bbbboooo ooooWrite EEPROMMemory1100 0000xxxx aaaabbbb bbbbiiii iiiiRead Lock bits0101 10000000 0000xxxx xxxxxxoo ooooWrite Lock bits1010 1100111x xxxxxxxx xxxx11ii iiiiRead Signature Byte0011 0000xxxx xxxxxxxx xxbboooo ooooWrite Fuse bits1010 11001010 0000xxxx xxxxiiii iiiiSet bits = “0” to program, “1” to unprogram.See Table 119 on page 290 for details.Write Fuse High Bits1010 11001010 1000xxxx xxxxiiii iiiiSet bits = “0” to program, “1” to unprogram.See Table 118 on page 290 for details.Write Extended Fusebits1010 11001010 0100xxxx xxxxxxxx xxiiSet bits = “0” to program, “1” to unprogram.See Table 119 on page 290 for details.Read Fuse bits0101 00000000 0000xxxx xxxxoooo ooooRead Fuse bits.
“0” = programmed, “1” =unprogrammed. See Table 119 on page290 for details.Read ExtendendFuse bits0101 00000000 1000xxxx xxxxoooo ooooRead Extended Fuse bits. “0” = pro-grammed,“1” = unprogrammed. See Table 119 onpage 290 for details.Read Fuse High Bits0101 10000000 1000xxxx xxxxoooo ooooRead Fuse high bits. “0” = pro-grammed, “1” =unprogrammed. See Table 118 on page290 for details.Read Calibration Byte0011 1000xxxx xxxx0000 00bboooo ooooRead Calibration Byte o at address b.Note:OperationRead H (high or low) data o from Programmemory at word address a:b.Write H (high or low) data i to ProgramMemory page at word address b.
Data lowbyte must be loaded before data high byte isapplied within the same address.Write Program Memory Page at address a:b.Read data o from EEPROM memory ataddress a:b.Write data i to EEPROM memory at addressa:b.Read Lock bits. “0” = programmed, “1” =unprogrammed. See Table 115 on page288 for details.Write Lock bits.
Set bits = “0” to program Lockbits. See Table 115 on page 288 for details.Read Signature Byte o at address b.a = address high bitsb = address low bitsH = 0 - Low byte, 1 - High Byteo = data outi = data inx = don’t care3072467M–AVR–11/04SPI Serial ProgrammingCharacteristicsFor characteristics of the SPI module, see “SPI Timing Characteristics” on page 325.Programming Via theJTAG InterfaceProgramming through the JTAG interface requires control of the four JTAG specificpins: TCK, TMS, TDI, and TDO.
Control of the Reset and clock pins is not required.To be able to use the JTAG interface, the JTAGEN fuse must be programmed. Thedevice is default shipped with the Fuse programmed. In addition, the JTD bit inMCUCSR must be cleared. Alternatively, if the JTD bit is set, the external reset can beforced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pinsare available for programming.
This provides a means of using the JTAG pins as normalport pins in running mode while still allowing In-System Programming via the JTAGinterface. Note that this technique can not be used when using the JTAG pins forBoundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated forthis purpose.As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.Programming Specific JTAGInstructionsThe instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for Programming are listed below.The OPCODE for each instruction is shown behind the instruction name in hex format.The text describes which data register is selected as path between TDI and TDO foreach instruction.The Run-Test/Idle state of the TAP controller is used to generate internal clocks.
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