ATmega128 (961732), страница 56
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The parameters in the figure above are given in Table on page 286.If no Boot Loader capability is needed, the entire Flash is available for application code.The Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection.The user can select:•To protect the entire Flash from a software update by the MCU•To protect only the Boot Loader Flash section from a software update by the MCU•To protect only the Application Flash section from a software update by the MCU•Allow software update in the entire FlashSee Table 108 and Table 109 for further details.
The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a chiperase command only. The general Write Lock (Lock bit mode 2) does not control theprogramming of the Flash memory by SPM instruction. Similarly, the generalRead/Write Lock (Lock bit mode 3) does not control reading nor writing by LPM/SPM, ifit is attempted.2772467M–AVR–11/04Table 108.
Boot Lock Bit0 Protection Modes (Application Section)(1)BLB0 modeBLB02BLB01111No restrictions for SPM or LPM accessing the Applicationsection.210SPM is not allowed to write to the Application section.0SPM is not allowed to write to the Application section, andLPM executing from the Boot Loader section is notallowed to read from the Application section. If interruptvectors are placed in the Boot Loader section, interruptsare disabled while executing from the Application section.1LPM executing from the Boot Loader section is notallowed to read from the Application section.
If interruptvectors are placed in the Boot Loader section, interruptsare disabled while executing from the Application section.304Note:0Protection1. “1” means unprogrammed, “0” means programmedTable 109. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)BLB1 modeBLB12BLB11111No restrictions for SPM or LPM accessing the Boot Loadersection.210SPM is not allowed to write to the Boot Loader section.0SPM is not allowed to write to the Boot Loader section,and LPM executing from the Application section is notallowed to read from the Boot Loader section. If interruptvectors are placed in the Application section, interrupts aredisabled while executing from the Boot Loader section.1LPM executing from the Application section is not allowedto read from the Boot Loader section.
If interrupt vectorsare placed in the Application section, interrupts aredisabled while executing from the Boot Loader section.304Note:0Protection1. “1” means unprogrammed, “0´means programmedEntering the Boot Loader Entering the Boot Loader takes place by a jump or call from the application program.This may be initiated by a trigger such as a command received via USART, or SPI interProgramface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset VectorReset is pointing to the Boot Flash start address after a reset.
In this case, the BootLoader is started after a reset. After the application code is loaded, the program canstart executing the application code. Note that the fuses cannot be changed by the MCUitself. This means that once the Boot Reset Fuse is programmed, the Reset Vector willalways point to the Boot Loader Reset and the fuse can only be changed through theserial or parallel programming interface.Table 110.
Boot Reset Fuse(1)BOOTRSTNote:278Reset Address1Reset Vector = Application Reset (address $0000)0Reset Vector = Boot Loader Reset (see Table 112 on page 286)1. “1” means unprogrammed, “0´means programmedATmega1282467M–AVR–11/04ATmega128Store Program MemoryControl and Status Register –SPMCSRThe Store Program Memory Control and Status Register contains the control bitsneeded to control the Boot Loader operations.Bit76543210SPMIERWWSB–RWWSREBLBSETPGWRTPGERSSPMENRead/WriteR/WRRR/WR/WR/WR/WR/WInitial Value00000000SPMCSR• Bit 7 – SPMIE: SPM Interrupt EnableWhen the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), theSPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as longas the SPMEN bit in the SPMCSR Register is cleared.• Bit 6 – RWWSB: Read-While-Write Section BusyWhen a Self-Programming (page erase or page write) operation to the RWW section isinitiated, the RWWSB will be set (one) by hardware.
When the RWWSB bit is set, theRWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bitis written to one after a self-programming operation is completed. Alternatively theRWWSB bit will automatically be cleared if a page load operation is initiated.• Bit 5 – Res: Reserved BitThis bit is a reserved bit in the ATmega128 and always read as zero.• Bit 4 – RWWSRE: Read-While-Write Section Read EnableWhen Programming (page erase or page write) to the RWW section, the RWW sectionis blocked for reading (the RWWSB will be set by hardware).
To re-enable the RWWsection, the user software must wait until the programming is completed (SPMEN will becleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, thenext SPM instruction within four clock cycles re-enables the RWW section. The RWWsection cannot be re-enabled while the Flash is busy with a page erase or a page write(SPMEN is set).
If the RWWSRE bit is written while the Flash is being loaded, the Flashload operation will abort and the data loaded will be lost.• Bit 3 – BLBSET: Boot Lock Bit SetIf this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 andthe address in the Z-pointer are ignored. The BLBSET bit will automatically be clearedupon completion of the lock bit set, or if no SPM instruction is executed within four clockcycles.An LPM instruction within three cycles after BLBSET and SPMEN are set in theSPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 inthe Z-pointer) into the destination register.
See “Reading the Fuse and Lock Bits fromSoftware” on page 283 for details.• Bit 2 – PGWRT: Page WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles executes page write, with the data stored in the temporary buffer. Thepage address is taken from the high part of the Z-pointer. The data in R1 and R0 areignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPMinstruction is executed within four clock cycles.
The CPU is halted during the entire pagewrite operation if the NRWW section is addressed.• Bit 1 – PGERS: Page EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles executes page erase. The page address is taken from the high part of2792467M–AVR–11/04the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear uponcompletion of a page erase, or if no SPM instruction is executed within four clock cycles.The CPU is halted during the entire page write operation if the NRWW section isaddressed.• Bit 0 – SPMEN: Store Program Memory EnableThis bit enables the SPM instruction for the next four clock cycles.
If written to onetogether with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPMinstruction will have a special meaning, see description above. If only SPMEN is written,the following SPM instruction will store the value in R1:R0 in the temporary page bufferaddressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit willauto-clear upon completion of an SPM instruction, or if no SPM instruction is executedwithin four clock cycles. During page erase and page write, the SPMEN bit remains highuntil the operation is completed.Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in thelower five bits will have no effect.Addressing the FlashDuring SelfProgrammingThe Z-pointer together with RAMPZ are used to address the SPM commands. Fordetails on how to use the RAMPZ, see “RAM Page Z Select Register – RAMPZ” onpage 12.15141312111098ZH (R31)BitZ15Z14Z13Z12Z11Z10Z9Z8ZL (R30)Z7Z6Z5Z4Z3Z2Z1Z076543210Since the Flash is organized in pages (see Table 123 on page 293), the programcounter can be treated as having two different sections.
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