Double estimator. A new receiver principle for tracking BOC signals (797924), страница 2
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While always subject to jitterfrom additive noise (and interference), asp ring 2008cross sectionχ(τ* – τ,0)2TS–∞+∞τ*τProjection of the new correlation forBOCs(2f, f)FIGURE 6InsideGNSS29double estimatorRepeatBOC signalcontinueb(t–τ)delay τtrial subcarrier replicaTStshift ±TS/2trial delayτ* ~ τ + nTStrial code replicashift ±TCtrial delayτ~τFIGURE 7TCRepeatImplementing the Conceptperiod TPMaximum correlation allowing redundancy in subcarrier shifts for BOCs(2f, f)steady state will tend to a joint or doubleestimate, looking for the nearest peakidentified according to Equation 3estimates must lie between limits as inEquation 5A Different InterpretationHere the estimate has relativelygreater r.m.s jitter (for a given input C/N0and loop bandwidth) because it derivessolely from the code modulation.
It is,however, unambiguous — just as if wehad the standard PSK modulation. Theindependent estimate has relativelyless r.m.s jitter under same assumptionsbecause it derives from the faster subcarrier modulation. However, this estimateis ambiguous because the integer n isarbitrary and initially unknown (withina range).Surely, however, the two estimatescan be combined instantaneouslyaccording to Equation 4,thus generating an unambiguous single estimate + whose accuracy fullyexploits the benefit of subcarrier modulation characteristic of BOC. It shouldbe noted from Figure 6 that in cross-section the periodic sub-carrier correlationis infinite in extent, and its peaks are allthe same amplitude — quite unlike thestandard ( ) correlation normally associated with BOC (as represented on theleft side of Figure 4 ).
Consequently thequality of the estimate is the same, whatever the rounded integer value.The correction by an integer multiple of sub-chip width TS requires thatthe noisy difference between the two30 InsideGNSS choices where to line up optimally onthe incoming BOC signal.As far as we know, none of the manyother published paper and patent applications attempting to solve the BOCtracking problem have appreciated andexploited this idea. We could identifya principle of correlation by subcarrierredundancy.Another way of visualizing the situationis presented in Figure 7. Given an inputBOC signal (in red), the aim is always tocorrelate that signal with a replica having as close a time alignment on thatsignal as possible. But when the replicais separated into its two components (inblue), the shifts needing to be applied tothe two trial delays need not be the same,and yet a signal-to-noise optimal, i.e.,maximum, correlation is still achieved.Always assuming a successful priorsearch that has already achieved somesignificant but not maximum correlation, then the code component mustshift its delay estimate as usual to a correct alignment and may have to moveup to ±TC from whatever was the initialsearch value.
But the subcarrier component needs to shift its delay estimate nomore than half a sub-chip width, i.e., ±TS/2, in order to achieve perfect alignmenton the signal.Estimation theorists should notethat, provided Equation 3 is satisfied,the resulting correlation — whethergiven a two-dimensional interpretationor not — is signal-to-noise optimal forany arbitrary integer shifts of subcarriersub-chips.The trick is to exploit the fact that thesub-carrier component can be shiftedby an integer number of sub-chips andyet the overall correlating waveformremains physically unaltered.
The subcarrier component replica has endlesssp ring 2008It is one thing to have a theory and quiteanother thing to make it work. Practically, we need to show that the acquisition to a peak can be mechanized in asimple manner in a receiver design andthat this can be automatically combinedwith phase or frequency acquisition onthe carrier.
Moreover, the system mustwork when the BOC signal is buriedin noise and it must reject interferencefrom many other competing BOC signals embodying different codes.It turned out to be a simple matter torealize all these things in a receiver bygeneralizing from two to three embedded interactive loops. As in the standardtwo-loop system for PSK/GPS, a phaselocked loop (PLL) or frequency-lockedloop (FLL) exists with which to track thecarrier; and a delay-locked loop (DLL)to track the code. But a BOC-capablereceiver based on the double estimatingconcept as described here must additionally provide a subcarrier-lockedloop (SLL) to track the subcarrier component.The conventional principle of providing early and late gate correlationscontinues to be employed but is nowgeneralized across two dimensions, provided by the DLL and the SLL.
These twoloops separately generate the independent delay estimates as theory requires.The third PLL (or FLL) independentlytracks the carrier.Convergence of any one loopdepends on successful convergence ofthe other two, because all three loopsrun interactively and cooperatively.The “independence” applies only to theemergence of the two independent delayestimates and the one carrier phase/frequency estimate.
Physically the systemis integrated as one entity.www.insidegnss.comFigure 8 shows the characteristic featuresInputAutomaticof a practical system. A BOC-modulatedGain Controltriple-loop double estimator(AGC)signal input feeds a right-hand circularlypolarized antenna and passes into a prePreAnalogue toDownu(t)amplifier that filters the received signal andamplifierDigitalconverterLNAConverterASICincorporates a low noise amplifier (LNA) toMicrooramplify the received signal.procesFFGAThe LNA effectively sets the receiver’ssorcorrelatornoise figure, normally around 2 dB, andReferencec(t)provides about 30 dB gain.
The pre-amplioscillatorfier feeds the filtered, amplified signal to adown-converter for a first stage down-conoptimal delayversion of the signal to a suitable intermediate frequency (IF). The signal is down- FIGURE 8 Practical structure of input to and output from the triple-loop double-estimatorconverted in multiple stages and filtered toeliminate unwanted image signals.The down-converter feeds an analog-to-digital converter(ADC). This can quantize the signal to one, two, or more bits.Typically, if the ADC uses multi-bit quantization, the receiverAfter mixing the input signal, using multipliers, I and Qincorporates an automatic gain control (AGC) circuit to main(in phase and quadrature) signals are derived (neglecting additain proper distribution of the signal across the quantizationtive noise and other BOC signals simultaneously present) as inlevels.
A reference oscillator provides a clock signal c(t). FromEquation 7.the ADC a digital signal u(t) goes to the double estimator ofthe delay τ between transmission and reception of the receivedsignal.The receiver includes a correlator stage and a processingA subcarrier DCO uses the clock signal to generatestage. In hardware the correlator stage comprises either anPrompt (P), Early (E), and Late (L) gate subcarrier referenceapplication specific integrated circuit (ASIC) or a field prosignals,andrespecgrammable gate array (FPGA). The processing stage can be atively, where is a trial subcarrier delay and TDS is the totalmicroprocessor that outputs a delay estimate.separation between the E and L gates.Figure 9 provides a more detailed functional description.
ItHere we maintain the convention that TDS = TS. Similarly, ashows the simplest possible coherent system for deriving andcode DCO uses the clock signal to generate P, E, and L gate codeprocessing the error signals, that is, CELP (coherent early-latereference signals,and,processing). We should emphasize that a triple-loop implemenrespectively, where is a trial code delay and TDC is the totaltation will support all the other usual choices of coherent andseparation between E and L gates. The separation TDC can benon-coherent gate processing and discriminator principles, forselected in the range TS ≤ TDC ≤ TC.example NELP (non-coherent early–later processing).The correlator block continues by multiplying the I and QThe correlator elements are contained within subsectionssignals with appropriate combinations of the P, E, and L gateof Figure 9 identified by the dotted borders.
The remainder issubcarrier reference signals and the P, E, and L gate code referthe processing stage. Colors help to identify the underlyingence signals in order to generate six demodulated signals vIII(t),processes. The signal flow is in red, reference and clock signalsvIEI(t), vILI(t), vIIE(t), vIIL(t), and vQII(t) as in Equations 8.are in blue, feedback and processed error signals are in green,while the final signal processing is in gold.The Concept in OperationThe input signal u(t) has been described according to Equation 1. A clock or reference c(t) is also needed.
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