Advanced global navigation satellite system receiver design (797918), страница 3

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..................................................................................................................162Figure 7-16, Spectrum analyser plot of BOC(1,1) from IF signal generator with noise............................................................................................................................162Figure 8-1, SGR receiver components.......................................................................165Figure 8-2, Frequency plan for GP2015 ....................................................................165Figure 8-3, Histogram of sampled signals from the GP2015 ....................................166Figure 8-4, GP2021 block diagram [Zarlink 2001] ...................................................167Figure 8-5, GP2021 tracking module diagram [Zarlink 2001] ..................................168Figure 8-6, Interrupt service routine for SGR receivers ............................................169Figure 8-7, SGR noise floor with no signal present...................................................170Figure 8-8, Plot combined search correlation wSSGR (shown in blue) ........................171Figure 8-9, First order FLL........................................................................................172Figure 8-10, Second order PLL .................................................................................174Figure 8-11, Prototype IF GNSS receiver..................................................................179Figure 8-12, Frequency plan for receiving MFUU signals........................................181Figure 8-13,Top level FPGA correlator architecture.................................................183Figure 8-14, IF receiver tracking channel..................................................................183Figure 8-15, Interrupt driven acquisition and tracking for PSK signals ....................186Figure 8-16, Interrupt driven acquisition and tracking sequence for BOC signals ...188Figure 9-1, Prototype receiver GPS PSK test setup...................................................191Figure 9-2, Distribution of digital AGC ....................................................................192Figure 9-3, IF receiver noise floor with no signal present (50 MHz sampling) ........193Figure 9-4, Typical PIF receiver output in GPS operation ........................................193Figure 9-5, Zero baseline test between IF receiver and SGR-05...............................196Figure 9-6, Pseudorange minus integrated carrier phase ...........................................197Figure 9-7, IQ plot from the PIF receiver: a) 45 dB-Hz b) 34 dB-Hz .......................198Figure 9-8, Comparison of PIF receiver estimated and theoretical carrier to noisedensities for........................................................................................................199Figure 9-9, Comparison of PIF receiver estimated and theoretical code tracking jitterfor.......................................................................................................................200Figure 9-10, Measurement offset due to asymmetric BOC(1,1) signal.....................202Figure 9-11, Typical PIF receiver display for BOC signals ......................................203Figure 9-12, Comparison of PIF receiver estimated and theoretical carrier to noisedensities for........................................................................................................204Figure 9-13, Example timing jitter of DLL and SLL loops .......................................205Figure 9-14, Comparison of PIF receiver estimated and theoretical code tracking jitterfor.......................................................................................................................206Figure 10-1, LEON3 architectural components [Gaisler 2006].................................209Figure 10-2, LEON3 processor with GNSS correlator..............................................209Figure 10-3, GPS testing of the single-chip receiver.................................................210Figure 10-4, Frequency plan for GP2015 ..................................................................211Figure 10-5, Frequency plan for Nemerix NJ1006A RF front end............................212Figure 10-6, I/Q plot of Galileo E1 signal with code states (ignoring data modulation,m = 0.6155) ........................................................................................................213Figure 10-7, I/Q plot of Galileo E1 signal from the receiver perspective .................213Figure 10-8, Elevation and azimuth of the Giove-A pass on the 26th of June 2006 ..216Figure 10-9, I/Q plot taken from Giove-A while in PLL mode.................................216Figure A-1, Tiered code hierarchical structure ..........................................................A-1Figure C-1, Slope of output correlation ...................................................................C-11Figure D-1, Dot product discriminator characteristic ................................................D-2Figure D-2, SGR DLL loop bandwidth and timing jitter against input C/N0 ............D-3Figure D-3, SGR DLL pseudorange noise and receiver estimated SNR(dB-kHz)....D-4Figure E-1, BOC(2×fC, fC) false-lock example with BJ gates....................................

E-1Figure E-2, Simulation of BJ threshold with uncorrelated noise samples ................. E-2Figure E-3, Worse case VE and VL count values for BOC(2×fC, fC) with uncorrelatedsignal to noise of 10 dB per correlation ............................................................. E-3Figure E-4, Simulation of BJ threshold with correlated noise samples ..................... E-4Figure E-5, Worse case VE and VL count values for BOC(2×fC, fC) with correlatednoise samples, signal to noise of 10 dB per correlation.....................................

E-5Figure F-1, Noise synthesis........................................................................................ F-1Figure F-2, Power spectrum with ND = 2 noise decimation...................................... F-6Figure F-3, Power spectrum with ND = 4 noise decimation...................................... F-7Figure F-4, Spectral plots of BOC(1, 1) signal (red) and digital noise (blue) ......... F-10Figure F-5, Spectral plots of BOC(10, 5) signal (red) and digital noise (blue) .......

F-10Figure H-1, Delay line subtractor for sBOC(1,1) ......................................................H-1Figure H-2, Delay line subtractor for cBOC(1,1) ......................................................H-3Figure I-1, AltBOC 8-PSK I/Q plot............................................................................ I-1LIST OF TABLESTable 3-1, Link budget for GPS satellites....................................................................37Table 3-2, Future GPS signals [GPS ICD 2007] .........................................................38Table 3-3, Galileo signals [ESA and GJU 2006].........................................................45Table 3-4, Galileo codes [ESA and GJU 2006]...........................................................46Table 3-5, Received power levels of Galileo signals [ESA and GJU 2006] ...............49Table 4-1, Timing jitter of BOC signals ......................................................................65Table 5-1, Costas PLL discriminators .........................................................................86Table 5-2, FLL discriminators .....................................................................................87Table 5-3, DLL discriminators ....................................................................................90Table 5-4, Hardware requirements of BOC search techniques....................................99Table 5-5, Acquisition times of the MGD discriminators and the SSB technique forBOC(2, 1), BL = 1 Hz, C/N0 = 24 dB-Hz ...........................................................105Table 5-6, Acquisition times of the BJ and SSB for BOC(2, 1), BL = 1 Hz, C/N0 = 24dB-Hz.................................................................................................................109Table 5-7, BJ parameters for BOC(2×fC, fC) under false-lock conditions .................111Table 5-8, Acquisition times of the BJ and SSB for BOC(6, 1), BL = 1 Hz, C/N0 = 24dB-Hz.................................................................................................................112Table 5-9, Symmetric and asymmetric BOC(2×fC, fC) peak values ..........................114Table 5-10, Hardware requirements of BOC tracking techniques.............................118Table 6-1, Costas PLL discriminators for the DE BOC receiver ..............................127Table 6-2, SLL discriminators for the DE BOC receiver ..........................................127Table 6-3, Coherent DLL discriminators for the DE BOC receiver..........................128Table 6-4, Acquisition times of the DE BOC receiver, BJ algorithm and the SSBtechnique for BOC(6, 1), BL = 1 Hz, C/N0 = 24 dB-Hz.....................................136Table 6-5, Hardware requirements of BOC tracking techniques...............................144Table 7-1, Relative signal powers of interplex modulated GNSS signals .................154Table 7-2 Example DAC amplitude mapping for interplex modulated GNSS signals............................................................................................................................155Table 8-1, SGR receiver models................................................................................164Table 8-2, 2-bit mapping by the GP2015...................................................................166Table 8-3, Mean square accumulation values over one carrier cycle ........................170Table 8-4, Predicted future SSTL receiver versions..................................................179Table 8-5, IF receiver hardware requirements per tracking channel .........................184Table 8-6, Xilinx Virtex II FPGA utilisation for PSK and BOC channels................185Table 8-7, Loop parameters and update equations ....................................................189Table 10-1, Galileo E1 PRN codes on Giove-A ........................................................214Table 10-2, Search times............................................................................................215Table D-1, DLL discriminators for PSK signals .......................................................D-1Table I-1, Example 8-bit DAC mapping.....................................................................

I-1Table I-2, AltBOC lookup table.................................................................................. I-2ABBREVIATIONSADCAGCAltBOCAMBAASICBOCBPSKC/ACASMCBOCCFICOTSCWDACDCMDCODEDLLEESAESTECFECFFTFLLFPGAGCLKGEOGETRGJUGNSSGPSHDLIIFIMPIOBLLCLEOLFSRLNALUTMAGMBOCMEOMFUUAnalogue to Digital ConverterAutomatic Gain ControlAlternate Binary Offset CarrierAdvanced Microprocessor Bus ArchitectureApplication Specific Integrated CircuitBinary Offset CarrierBinary Phase Shift KeyedCoarse AcquisitionCoherent Adaptive Subcarrier ModulationComposite Binary Offset CarrierCustomer Furnished ItemCommercial Off The SelfContinuous WaveDigital to Analogue ConverterDigital Clock ModuleDigitally Controlled OscillatorDouble EstimatorDelay Locked LoopEarlyEuropean Space AgencyEuropean Space Research and Technology CentreForward Error CorrectionFast Fourier TransformFrequency Locked LoopField Programmable Gate ArrayGlobal ClockGeostationary Earth OrbitGalileo Experimental Test ReceiverGalileo Joint UndertakingGlobal Navigational Satellite SystemGlobal Positioning SystemHardware Description LanguageIn-phaseIntermediate FrequencyInter-Modulated ProductInput Output BlockLateInductor CapacitorLow Earth OrbitLinear Feedback Shift RegisterLow Noise AmplifierLook Up TableMagnitudeMultiplexed Binary Offset CarrierMedium Earth OrbitModulator Frequency Up-converter UnitMGDMSBNMGUPPCPIFPLLPRNPSDPSKPVTQQPSKRFRHCPRTSAWSCCSGRSLLSNRSSBSSCSSTLSVTCXOTMBOCTTFFTWTUARTVEVLMultiple Gate DiscriminatorMost Significant BitNavigational Message Generation UnitPromptPersonal ComputerPrototype Intermediate FrequencyPhase Locked LoopPseudo Random NoisePower Spectral DensityPhase Shift KeyingPosition Velocity TimeQuadratureQuadrature Phase Shift KeyingRadio FrequencyRight-Hand Circularly PolarisedRadiation TolerantSub-Carrier CancellationSpace GNSS ReceiverSub-carrier Locked LoopSignal to Noise RatioSingle Side-BandSurrey Space CentreSurrey Satellite Technology LimitedSpace VehicleTemperature Controlled Crystal OscillatorTime Multiplexed Binary Offset CarrierTime To First FixTravelling Wave TubeUniversal Asynchronous Receiver-TransmitterVery EarlyVery LateSYMBOL LISTΛΛVφˆτˆa~ (t )w′∆φˆ~b (t )Idealised PRN code correlation functionPulse equivalent to a PRN code chipPSK equivalent early minus late discriminator functionReceiver estimated carrier phaseReceiver DLL estimated PRN code delayOrthogonal PRN code sequenceTime adjacent correlation resultReceiver estimated carrier phase difference between epochsOrthogonal BOC modulated code sequenceIdealised BOC correlation functionIdealised BOC discriminator function~s (t )τˆ *d̂τˆ +ωλκΣσεη∆αφτρ∆τ∆φθ(t)τ*DCOω0τDCOφDCO∆fωnσNβRλSCAa(t)bb(t)BdBLBScCC(t)CdLiCrLid(t)eφeωeτeτ*fφfωOrthogonal sub-carrier waveformReceiver SLL estimated code delayNavigational data estimateCorrected SLL delay estimateCarrier frequencyCarrier wavelengthSpectral separation coefficientMean square timing timing jitterNormalised standard deviation of timing jitterTiming errorOne sided white noise densityNormalised discriminator spacingCoefficient of reflectionGeneral phase shift termTime delay of PRN code sequencePseudorangePRN code delay errorCarrier phase difference between epochsComposite phase modulation introduced for interplex modulationSub-carrier DCO phase (ms)Centre frequency of IF signalCode DCO phase (ms)Carrier DCO phaseFrequency errorNatural loop frequencyStandard deviation of the synthesised noiseTwo sided receiver front-end bandwidthSub-carrier wavelengthSignal AmplitudePRN code sequenceNormalised receiver front-end bandwidthBOC modulated waveformData bandwidth (two-sided)Loop bandwidthSignal bandwidth (two-sided)Speed of lightCarrier powerComposite modulation of BOC sub-carrier and/or PRN code sequenceCode lock indicatorCarrier lock indicatorNavigational data messagePLL estimated carrier phase errorFLL estimated carrier frequency errorDLL estimated PRN code delay errorSLL estimated PRN code delay errorIntegrated carrier phase errorIntegrated carrier frequency errorfCfDACfNfSfSGGτGFi(t)ICPISCPkKkφkωkφ*kω*KFDKPDKCDKDCOKNKSCLDmnNn(t)N0NFNHCPpRS(ω)s(t)S(t)ScLisqc(t)TTτTτ*t(m)TCTDTDCTRtrc(t)Trstrs(t)PRN code chipping rateSampling frequency of DACUpdate frequency of noise samplesBOC sub-carrier frequencySampling frequencyLFSR polynomialCorrelation gain with PRN code delay errorCorrelation gain with frequency errorInterfering signalsIntegrated carrier phaseIntegrated sub-carrier phaseLoop gainTotal number of early late gatesCarrier to code Doppler scaling factor for a coherent receiverCarrier to code Doppler scaling factor for a incoherent receiverCarrier to sub-carrier Doppler scaling factor for a coherent receiverCarrier to sub-carrier Doppler scaling factor for a incoherent receiverFrequency discriminator gainPhase discriminator gainCode discriminator gainDCO gainRatio between the DAC sampling rate and noise update rateRatio between the DAC sampling rate and PRN code rateLength of data bit (ms)Modulation indexLFSR lengthNumber of chips in PRN code sequenceAdditive noiseNoise densityTheoretical receiver noise floor valueNumber of half chip per code epochSignal powerInteger count of early late gatesAutocorrelation functionSignal power spectral densitySquare sub-carrier waveformPSK signal representationSub-carrier lock indicatorSquare cosine waveformIntegration timeTransmit time from DLLTransmit time from SLLCross correlation valuesPRN code chip periodEarly to late discriminator spacingCode loop discriminator spacingReceiver estimated timeTriangular cosine functionTrapezoidal sine functionTriangular sine functionTSTTu(t)v(t)ww(t)wSX(s)x(t)XCCXDXEXHCXSCY(s)y(t)Z[k]Sub-chip periodTransmission timeReceived signal representationReceived signal multiplied by receiver generated replicasCorrelation resultNoise sampleSearch correlationInput to filter (s domain)Input to filter (time domain)Carrier cycle counterData bit counter valueEpoch counter valueHalf chip counter valueSub-carrier cycle counterOutput of filter (s domain)Output of filter (time domain)Random number at sample kAcknowledgementsFirst and foremost I would like to express my gratitude for the significant theoreticalsupport offered by my academic supervisor Dr Stephen Hodgart.

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