62746 (588822), страница 11

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.section/dm seg_dmdata;

.var lpf[2];

.var n_2;

.var Uinp;

.section/pm seg_pmdata;

//.var Porog[2]={0x03D8,0x7C28};

.VAR coeff1 [coeflen]="Dat\280_el4.dat";

.var Porog1 [5]={0x7f,0xe7,0x17f,0x1e7,0x23f};

.var Porog2 [5]={0x01c,0x02a,0x040,0x070,0xae};

/*.var Coeff2a[11]="Dat\20k_2.dat";

.var Coeff2b[11]="Dat\19_5k_2.dat";

*/.var Coeff2c[10]="dat\17_4k.dat"; //="Dat\19k_2.dat";

/*.var Coeff2d[11]="Dat\18_5k_2.dat";

.var Coeff2e[11]="Dat\18k_2.dat";

.var Coeff3a[6]="Dat\19k_1.dat";

.var Coeff3b[6]="Dat\18k_1.dat";

*/.var Coeff3c[5]="dat\x.dat"; /*="Dat\20k_1.dat";

.var Coeff3d[6]="Dat\18_5k_1.dat";

.var Coeff3e[6]="Dat\19_5k_1.dat";

*/

//.var Fir_flt[1001*2]="Dat\fir.dat";

.section/pm IVint4;

ena sr;

dis int;

mx1=iopg;

mx0 = 0x8001;

mr1 = 0x1;

my0=dmpg1;

dmpg1=0;

//ax0 = 0x1;

/* write the Configuration words for the 2nd transfer, setting the Ownership and DMA enable bits */

iopg = Memory_DMA_Controller_Page;

my1 = 0x8003;

io(DMACW_IRQ) = mr1; /* writing a 1 to this register clears the interrupt */

dm(_RD_DMA_CONFIG1)= mx0;

dm(_WR_DMA_CONFIG1)= my1;

io(DMACW_CPR) = mr1; /* Set the descriptor ready bit in both Write and Read channels */

io(DMACR_CPR) = mr1; /* to signal to the DMA engine that the ownership bit has been set */

dm(_RD_DMA_CONFIG2)= mx0;

dm(_WR_DMA_CONFIG2)= my1;

dm(_RD_DMA_CONFIG3)= mx0;

dm(_WR_DMA_CONFIG3)= my1;

my1 = 0x8007;

dm(_RD_DMA_CONFIG4)= mx0;

dm(_WR_DMA_CONFIG4)= my1;

//io(DMACW_CFG) = mx0;// /* enable DMA in both channels */

//io(DMACR_CFG) = mx0;//

iopg=mx1;

rti(db);

dmpg1=my0;

ena int;

.section/pm seg_pmcode;

.global ini_row,row,Start_DMA;

#define nsecs1 3

.global External_Port_Init;

External_Port_Init:

IOPG = External_Memory_Interface_Page;

ax0=0x38;

// ax1=b#0000000100010010;

ax1=b#0000001011100100;

// ax1=b#0000001111110110;

// || | ++++++---waitstates(2-0 for rd, 5-3 for wr),WaitStateMode (bits 7-6)

// || ++---------00-only ACK, 01 - Only waitStates 10 - both, 11 one of

// |+++-----------ClockDividerSelect bits 10-8: 000=1 : 101=32;

// +--------------WriteHoldEnable if 1 - enables extend the write data hold time by one cycle

IO(EMICTL)=ax0;

ax0=b#0000000001001001;

// ax0=b#0000110111111111;

IO(MS0CTL)=ax1;

IO(MS1CTL)=ax0;//ax1

IO(MS2CTL)=ax0;

IO(IOMSCTL)=ax0;

ax1=0x4001;

IO(MS3CTL)=ax0;

ax0=0xc080;

io(MEMPG10)=ax1;

io(MEMPG32)=ax0;

rts;

Start_DMA:

iopg = Memory_DMA_Controller_Page;

Характеристики

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