Лекция 2. Intel technologies for HPC Applications (Semin) (1186100), страница 2

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All products, computer systems, dates, and figures specified are preliminary based on currentMaximum Theoretical SpeedupsPositioning of SIMD FeaturesFully automatic vectorizationEase of useAuto vectorization hints (#pragma ivdep)SIMD feature (#pragma omp simd and simd functionannotation)SIMD intrinsic class (F32vec4 add)Vector intrinsic (_mm_add_ps())ASM code (addps)Programmer controlSample: Manual Vectorizationvoid vecmul(float *a, float *b, float *c, int n){for (int k=0; k<n; k++)c[k] = a[k] * b[k];}• For the following slide we make the following assumptions(otherwise, we’d run out of space)– Input and output data is properly aligned to 64 bytes– Vector length is a multiple of the vector length• If assumptions do not hold, add code to:– Peel off iterations 0..m to get rid of alignment issue– Have a vectorized loop to do the work– Peel off iterations n..N-1 to deal with remaining dataSample: Manual Vectorizationvoid vecmul(float *a, float *b, float *c, int n){• Loop unrolling by 16Vector registers(i.e.

vector length)__m512 va;__m512 vb;• Increment pointers__m512 vc;for (int i = 0; i < a->size; i += 16, a += 16, b += 16, c += 16) {va = _mm512_loadd(a, _MM_FULLUPC_NONE, _MM_BROADCAST_16X16, _MM_HINT_NONE);vb = _mm512_loadd(b, _MM_FULLUPC_NONE, _MM_BROADCAST_16X16, _MM_HINT_NONE);vc = _mm512_mul_ps(va, vb);_mm512_stored(vc, c, _MM_DOWNC_NONE, _MM_SUBSET32_16, _MM_HINT_NONE);}Vector instructions}SIMD Instructions / Vectorization• SSE: Streaming SIMD extension• SIMD: Single instruction, Multiple Data (Flynn’s Taxonomy)– e.g., SSE allows the identical treatment of 2 double, 4 floats and 4integers at the same timeSource vector aa3a1a2opb3Source vector bb1b2=a3 op b3a2 op b2a0b0Destination vectora1 op b1a0 op b0Vectorization: SSE Data Typesxmm register, 128 bit2x double4x float16x byte8x short4x integer322x integer64Evolution to Intel AVXymm register, 256 bitLane 1Lane 0SIMD Instructions on Intel MIC and AVX512zmm register, 512 bit/64 bytesAVX512 - Greatly increased register fileHigher throughputGreatly improved unrolling and inlining opportunities32 vector registers, 512b wide: zmm0 through zmm31– Overlaid on top of existing YMM arch state– Writing to xmm zeroes bits [511:128]– writing to ymm zeroes bits [511:256]SSEAVX2AVX-512YMM0-158 mask registers, 64b wide: k0 through k732 bytes– KNL only uses bits [15:0] though (PS,PD,D,Q)– EVEX.aaa=000 is an indicator of “no mask”– {k0} is illegal511256 255128 127ZMM0YMM0XMM0ZMM1YMM1XMM1063k7ZMM31YMM31XMM310k0k1ZMM03164 bytesXMM01516bytesAVX-512 F Designed for HPC• Promotions of many AVX and AVX2 instructions to AVX-512−−−32-bit and 64-bit floating-point instructions from AVXScalar and 512-bit32-bit and 64-bit integer instructions from AVX2• Many new instructions to speedup HPC workloadsQuadwordintegerarithmeticIncludinggather/scatterwith D/QwordindicesNewpermutationprimitivesBitmanipulationIEEE divisionand square rootTwo sourceshufflesVector rotateDPtranscendentalprimitivesCompress &ExpandUniversal ternarylogical operationMath supportNewtranscendentalsupportinstructionsNew maskinstructionsWider data vectorAVX-512AVX2float A[N], B[N], C[N]float A[N], B[N], C[N]for(i=0; i<8; i++){C[i] = A[i] + B[i];}VADDPS YMM0, YMM1, YMM2for(i=0; i<16; i++){C[i] = A[i] + B[i];}16 x 256-bit registersIn each register:8 float or 4 double8 integer or 4 long32 x 512-bit registersIn each register:16 float or 8 double16 integer or 8 longVADDPS ZMM0, ZMM1, ZMM2Masking – new feature in AVX8 new mask registers k0-k7Create mask:VCMPPS k1, zmm1, zmm2, immk1 = ..0101100111 /* 16 bits */VCMPPD k1, zmm1, zmm2, immk1 = ..01011001 /* 8 bits */Unmasked elements remainunchanged:VADDPD zmm1 {k1}, zmm2, zmm3Or zeroed:VADDPD zmm1 {k1} {z}, zmm2,zmm3Use mask:VADDPD dst {k1}, src1, src2dsta7a6a5a4a3a2a1a0src1b7b6b5b4b3b2b1b0src2c7c6c5c4c3c2c1c0k110111100dstb7+c7a6b5+c5 b4+c4 b3+c3 b2+c2a1a0dstb7+c70b5+c5 b4+c4 b3+c3 b2+c200Why masking?• Memory fault suppression– Vectorize code using masked load/store– Typical examples are if-conditional statements or loop remainders• Avoid spurious floating-point exceptions• Zeroing/merging– Use zeroing to avoid false dependencies VADDPD zmm1 {k1} {z}, zmm2, zmm3– Use merging to preserve unmasked values VADDPD zmm1 {k1} , zmm2, zmm3float A[N], B[N], C[N];for(i=0; i<16; i++){if (B[i] != 0)A[i] = A[i] / B[i];elseA[i] = A[i] / C[i];}VMOVUPS zmm2, A[16]VCMPPS k1, zmm0, BVDIVPSzmm1 {k1}{z}, zmm2, BKNOT k2, k1VDIVPSzmm1 {k2}, zmm2, CVMOVUPS A[16], zmm1Why Separate Mask Registers?• Don’t waste away real vector registers for vector of booleans• Separate control flow from data flow• Boolean operations on logical predicates consume lessenergy (separate functional unit)• Tight encoding allows orthogonal operand– Every instruction now has an extra mask operandEmbedded BroadcastBroadcast one scalar from memory into all vector elementslong A[N], B[N], CCfor(i=0; i<8; i++){if(A[i]!=0.0)B[i] = A[i] + C;}CCCCA7A6A5A4CCCCA3A2A1A0B3B2B1B0+=B7B6B5B4VADDPS zmm1 {k1}, zmm2, C {1to16}•••Scalars from memory are first class citizensBroadcast one scalar from memory into all vectorelements before operationMemory fault suppression avoids fetching the scalar ifno mask bit is set to 1VGATHER/VSCATTER Operationvgather v1{k2},[rax+v3]v3 = 3 0 1 2 5 4 2 1 2 0 3 0 3 6 2 15rax+06rax+17rax+28rax+39rax+4k2 = 1 1 1 0 0 1 1 0 1 1 0 0 0 0 1 1v1 = 8 5 6 0 0 9 7 0 7 5 0 0 0 0 7 6vscatter [rax+v3]{k2}, v1-- same as vgather, but in reverseEmbedded Rounding Control• Set Rounding Control– AVX2 and before – access MXCSR.RC– Saving, modifying and restoring MXCSR is usually slow and cumbersomeSTMXCSRMOVANDORMOVLDMXCSR[ESI]EAX,[ESI]AH,9FhAH,20h[ESI],EAX[ESI];store the MXCSR into memory;put into EAX;clear existing rounding bits (bits 13/14 of eax);set rounding down;put back into memory;and put that into processor ;• AVX-512 – define rounding control per instructionVADDPS ZMM1 , ZMM2, ZMM3 {rne-sae}– “Suspend All Exceptions”– Always implied by using embedded RC– NO MXCSR updates / exception reporting for any laneExpand & Compressdouble A[N], B[N], C[N];for(i=0; i<8; i++){if (B[i] != 0)VMOVUPD zmm2, A[8]VCMPPD k1, zmm0, B*dst++ = A[i];VCOMPRESSPD [dst] {k1}, zmm2}A1A2A3compressA0A5A6A7Zeroed in theregister formMask: k[] = 01110011A1expandA4A0A2A1A3A2A6A3A7A4All “X” are zeroed orremain unchangedMask: k[] =01110011XA0A1A2XXA3A4Quadword Integer ArithmeticUseful for pointer manipulation64-bit becomes a first class citizenRemoves the need for expensive SW emulation sequencesInstructionDescriptionVPADDQ zmm1 {k1}, zmm2, zmm3INT64 additionVPSUBQ zmm1 {k1}, zmm2, zmm3INT64 subtractionVP{SRA,SRL,SLL}Q zmm1 {k1}, zmm2, imm8INT64 shift (imm8)VP{SRA,SRL,SLL}VQ zmm1 {k1}, zmm2, zmm3INT64 shift (variable)VP{MAX,MIN}Q zmm1 {k1}, zmm2, zmm3INT64 max, minVP{MAX,MIN}UQ zmm1 {k1}, zmm2, zmm3UINT64 max, minVPABSQ zmm1 {k1}, zmm2, zmm3INT64 absolute valueVPMUL{DQ,UDQ} zmm1 {k1}, zmm2, zmm332x32 = 64 integer multiplyNote: VPMULQ and int64 <-> FP converts not in AVX-512 FMath SupportPackage to aid with Math library writing• Good value upside in financial applications• Available in PS, PD, SS and SD data types• Great in combination with embedded RCInstructionVGETXEXP{PS,PD,SS,SD}zmm1 {k1}, zmm2Obtain exponent in FP formatVGETMANT{PS,PD,SS,SD}zmm1 {k1}, zmm2Obtain normalized mantissaVRNDSCALE{PS,PD,SS,SD}zmm1 {k1}, zmm2, imm8Round to scaled integral numberVSCALEF {PS,PD,SS,SD}zmm1 {k1}, zmm2, zmm3X*2y , X <= getmant, Y <= getexpVFIXUPIMM{PS,PD,SS,SD}zmm1, zmm2, zmm3, imm8Patch output numbers based on inputsVRCP14{PS,PD,SS,SD}zmm1 {k1}, zmm2Approx.

reciprocal() with rel. error 2-14VRSQRT14{PS,PD,SS,SD}zmm1 {k1}, zmm2Approx. rsqrt() with rel. error 2-14VDIV{PS,PD,SS,SD}zmm1 {k1}, zmm2, zmm3IEEE divisionVSQRT{PS,PD,SS,SD}zmm1 {k1}, zmm2IEEE square rootNew 2-Source Shuffles2-Src ShufflesLong standing customer request• 16/32-entry table lookup (transcendental support)• AOS  SOA support, matrix transpose• Variable VALIGN emulationVSHUF{PS,PD}VPUNPCK{H,L}{DQ,QDQ}VUNPCK{H,L}{PS,PD}VPERM{I,D}2{D,Q,PS,PD}VSHUF{F,I}32X4150zmm110 11 220H’9G’…1098765zmm2F’ E’ D’C’B’A’HGF43zmm3EDCCAB’zmm1 H’AC’D’210CBABit ManipulationBasic bit manipulation operations on mask and vector operands• Useful to manipulate mask registers• Have uses in cryptography algorithmsInstructionDescriptionKUNPCKBW k1, k2, k3Interleave bytes in k2 and k3KSHIFT{L,R}W k1, k2, imm8Shift bits left/right using imm8VPROR{D,Q} zmm1 {k1}, zmm2, imm8Rotate bits right using imm8VPROL{D,Q} zmm1 {k1}, zmm2, imm8Rotate bits left using imm8VPRORV{D,Q} zmm1 {k1}, zmm2, zmm3/memRotate bits right w/ variable ctrlVPROLV{D,Q} zmm1 {k1}, zmm2, zmm3/memRotate bits left w/ variable ctrlVPTERNLOG – Ternary Logic Instruction• Mimics a FPGA cell– Take every bit of three sources to obtain a 3-bit index N– Obtain Nth bit from imm8VPTERNLOGDzmm0 {k2}, zmm15, zmm3/[rax], imm8Any arbitrary truth table of 3 values can beimplementedandor, andxor, vote, parity, bitwise-cmov, etc.each column in the right table corresponds to imm8S100001111S200110011S301010101ANDOR01010111VOTE (S1)?S3:S20001001100101111Imm8[7:0]src0[i]src1[i]src2[i]Dest[i]Motivation for Conflict Detection• Sparse computations are common in HPC, but hard tovectorize due to race conditions• Consider the “histogram” problem:for(i=0; i<16; i++) {index = vload &B[i]old_val = vgather A, indexnew_val = vadd old_val, +1.0vscatter A, index, new_val////////A[B[i]]++; }Load 16 B[i]Grab A[B[i]]Compute new valuesUpdate A[B[i]]• Code above is wrong if any values within B[i] are duplicated− Only one update from the repeated index would be registered!• A solution to the problem would be to avoid executing the sequence gatherop-scatter with vector of indexes that contain conflictsIteration 3Iteration 2Iteration 1Conflict Detection – how does it work?mask11111111indices93222787conflict-freemask11100110mask00011001indices93222787conflict-freemask00010001mask00001000indices9322278700001000conflict-freemaskConflict Free CodeCDI instr.for(i=0; i<16; i++){j = B[i];A[j]++;}j = vload &B[i]pending_elts = 0xFFFF;do {mask = conflict_free(j, pending_elts)val_A = vgather {mask} A, jval_A++vscatter A {mask}, j, val_Apending_elts ^= mask} while (pending_elts)VPCONFLICT{D,Q} zmm1{k1},zmm2/memVPBROADCASTM{W2D,B2Q} zmm1, k2VPTESTNM{D,Q} k2{k1}, zmm2,zmm3/memVPLZCNT{D,Q} zmm1 {k1}, zmm2/mem////////Grab A[j]Compute new valuesUpdate A[j]remove done idxVPCONFLICT instruction detects elements with previous conflicts in a vector of indexesAllows to generate a mask with a subset of elements that are guaranteed to be conflict freeSummary• Continuous demand for high performance computingsolution fuels innovation in architectures to address technicalchallenges• Intel offers highly optimized architectures for HPC solutions• AVX-512 is the greatest addition to x86 ISA family to drivecontinuous performance improvementsQuestions?.

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