Using_ModelSim (1162598), страница 4
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This list contains many well-knownsimulation tools, including ModelSim. From the drop-down list select ModelSim-Altera.Once a simulation tool is selected, EDA Netlist Writer settings become available. These settings configure QuartusII to produce input for the simulation tool. Quartus II will use these parameters to describe an implemented designusing a given HDL language, and annotate it with delay information obtained after compilation. The settings we candefine are the HDL language, simulation time scale that defines time step size for the simulator to use, the locationwhere the writer saves design and delay information, and others.
Set these settings to match those shown in Figure 24and click OK.With the EDA Tools Settings specified, we can proceed to compile the project in Quartus II. The compilation processsynthesizes, places, and routes the design, and performs timing analysis. Then it stores the compilation result in thesimulation directory for ModelSim to use. Take a moment to examine the files generated for simulation using a texteditor. The two main files are serial.vo, and serial_v.sdo.The serial.vo file is a Verilog file for the design. The file looks close to the original Verilog file, except that thedesign now contains a wide array of modules with a cycloneii_ prefix.
These modules describe resources on anAltera Cyclone II FPGA, on which the design was implemented using lookup tables, flip-flops, wires and I/O ports.The list of delays for each module instance in the design is described in the serial_v.sdo file.24Altera Corporation - University ProgramMay 2012U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus II 12.0Figure 24. Quartus II EDA simulation tool settings.5.2Running a Timing SimulationTo simulate the design using timing simulation we must create a ModelSim project. The steps are the same as inthe previous section; however, the project is located in the example/timing/simulation/modelsim subdirectory, andthe source file is serial.vo.
We do not need to include the serial_v.sdo file in the project, because a reference to itis included in the serial.vo file. Once you added the source file to the project, compile it by selecting Compile >Compile All.The next step in the simulation procedure is to place the ModelSim software in simulation mode. In the previoussection, we did this by selecting Simulate > Start Simulation..., and specifying the project name. To run a timingsimulation there is an additional step required to include the Altera Cyclone II device library in the simulation.This library contains information about the logical operation of modules with the cycloneii_ prefix. To include theCyclone II library in the project, select Simulate > Start Simulation... and select the Libraries tab as shown inFigure 25.Altera Corporation - University ProgramMay 201225U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus II 12.0Figure 25.
Including Altera Cyclone II library in ModelSim project.The Altera Cyclone II library is located in the altera/verilog/cycloneii directory in the ModelSim-Altera software.To add this library to your project, include the altera/verilog/cycloneii directory using the Add... button. Then, clickon the Design tab, select your project for simulation (tutorial > serial), and click OK.When the ModelSim software enters simulation mode, you will see a significant difference in the contents of theworkspace tabs on the left-hand side of the window as compared to when you ran the functional simulation.
Inparticular, notice the sim tab and the Objects window shown in Figure 26. The list of modules in the sim tab islarger, and the objects window contains more signals. This is due to the fact that the design is constructed usingcomponents on an FPGA and is more detailed in comparison to an abstract description we used in the previoussection of the tutorial.26Altera Corporation - University ProgramMay 2012U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus II 12.0Figure 26.
Workspace tabs and Objects window for timing simulation.We simulate the circuit by creating a waveform that includes signals sum, A, B, start (go), and resetn aliases asbefore. In addition, we include the clock, reg_sum|q, reg_A|q, and reg_B|q signals from the Objects window.Signals reg_A|q and reg_B|q are registers that store A and B at the positive edge of the clock. The reg_sum|q signalis a register that stores the resulting sum.Begin the simulation by resetting the circuit. To do this, set go and resetn signals to 0. Also, set the clock input tohave a period of 20 ns, whose first edge is a falling edge.
To run the simulation, set the simulation step to 20 ns andpress the Run button. The simulation result is shown in Figure 27.Altera Corporation - University ProgramMay 201227U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus II 12.0Figure 27.
Timing Simulation after 20 ns.To proceed with the simulation deassert the resetn signal by setting it to 1, and apply data to inputs A and B. Setthem to 143 and 57, and assign a value of 1 to the go input as described in the Functional Simulation section of thetutorial. Then run the simulation for a period of 20 ns, by pressing the Run button. The simulation result is shownin Figure 28.
Remember to change the radix of A, B, sum, and their corresponding registers to unsigned.28Altera Corporation - University ProgramMay 2012U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus II 12.0Figure 28. Timing Simulation after 40 ns.In Figure 28 the data is stored in registers reg_A|q and reg_B|q at the positive edge of the clock.
Notice that thesimulation indicated that the data in those registers changes some time after the positive edge of the clock, unlike inthe functional simulation. The reason for this difference are the delays in the circuit. We can use the zoom buttonsto see this more clearly.When we zoom in on the time when registers reg_A|q and reg_B|q change value, we see the register values changeas shown in Figure 29.
In the figure, register reg_B|q stabilizes on a value of 57 at time 32928 ps. This is 2928 psafter the positive edge of the clock appeared at the clock input. Part of the difference in times between the clock edgeand the change of data in register reg_B|q comes from the fact that the clock signal must travel from the input pinon the FPGA device to the registers. The other part of the time is due to the clock-to-Q time of the register, which isthe time it takes for a register to change output after it sees a positive edge on the clock input.Altera Corporation - University ProgramMay 201229U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus II 12.0Figure 29. Zoomed-in Timing Simulation after 40ns.Another interesting aspect of the timing simulation can also be observed in Figure 29.
Notice that register reg_B|qfirst changes value to 48 and a few picoseconds later assumes the value 57. This is because the clock signal does notget to every flip-flop at exactly the same time - this is called clock skew.6Concluding RemarksThis tutorial discussed the basic use of ModelSim simulator. We demonstrated how to perform a functional simulation using a user-written Verilog code, as well as a detailed timing simulation.
For the timing simulation, wepresented a simple method to generate design description using Altera Quartus II CAD software, which includes thelow-level design details and circuit delays.There are more advanced options for simulation available in ModelSim software. They can help automate and speedup the simulation of larger more complex designs. These features are covered in the tutorials provided with theModelSim tool, and are beyond the scope of this introductory tutorial.30Altera Corporation - University ProgramMay 2012U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS IN V ERILOG D ESIGNSFor Quartus II 12.0Copyright ©1991-2012 Altera Corporation.
All rights reserved. Altera, The Programmable Solutions Company, thestylized Altera logo, specific device designations, and all other words and logos that are identified as trademarksand/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in theU.S. and other countries. All other product or service names are the property of their respective holders. Alteraproducts are protected under numerous U.S. and foreign patents and pending applications, mask work rights, andcopyrights. Altera warrants performance of its semiconductor products to current specifications in accordance withAltera’s standard warranty, but reserves the right to make changes to any products and services at any time withoutnotice.
Altera assumes no responsibility or liability arising out of the application or use of any information, product,or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers areadvised to obtain the latest version of device specifications before relying on any published information and beforeplacing orders for products or services.This document is being provided on an ”as-is” basis and as an accommodation and therefore all warranties, representations or guarantees of any kind (whether express, implied or statutory) including, without limitation, warrantiesof merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed.Altera Corporation - University ProgramMay 201231.
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