Вводная лабораторная по временному анализу схем (Altera University Program) (1132232), страница 2
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When the slack is negative,the path takes too long to compute, and the timing is considered to violate the clock constraint. In this example, thedesired clock period was 1ns, and one of the paths in the circuit exceeded this constraint by 2.503ns. The timinganalysis details for a given path can be displayed in the two panes at the bottom of the report by clicking on one ofthe paths in the report, as shown in Figure 10.The bottom two sections of the report consist of identical sets of tabs. The tabs show path summary, statistics, datapath, and waveforms.
The left-hand side shows a set of components through which the path travels, including thedelays along the way, while the right-hand side shows the waveform that explains how the timing violation occurred.The waveform display is a useful tool in understanding the timing of a circuit. It includes both data delays on agiven path as well as clock delays to source and destination registers. At a glance, the information provided in thewaveform is comprehensive to experts, but may not be as intuitive to others. This is because the timing information8Altera Corporation - University ProgramJanuary 2011U SING T IME Q UEST T IMING A NALYZERFigure 10.
Detailed setup time information for a given register-to-register path.is shown with respect to the time when inputs appear at the input pin to an FPGA device. For example, the clocksignal shown in the first line is the signal at the pin of the device, and it arrives at the clock input of the sourceflip-flop later. In Figure 11 we show how to interpret the waveform information presented in Figure 10.In the figure, the first three waveforms show the clock signals for the source and destination flop-flops, along with atiming requirement - in this case 1ns.
The launch and latch edges of each clock are indicated by thick lines. The nexttwo waveforms in the figure show the same clock signals as they appear at the clock inputs of source and destinationflip-flops, with the launch and latch clock edges indicated appropriately. These two waveforms show the actual timethe data will be launched from and stored in flip-flops. Note that the Launch Clock at Source FF and Latch Clock atDestination FF waveforms in Figure 11 are shown for this explanation, but are not part of the screenshot in Figure 10.The Clock Delay in Figure 10 represents the time between the launch/latch edges at the pin of the device and at theclock inputs of the source/destination flip-flops.The next two waveforms, Data Arrival and Data Delay, show the time it will take a signal to propagate from sourceto destination.
Notice that Data Delay is measured from the positive edge of the clock named Launch Clock atSource FF. The second last waveform, called Data Required indicates the time when the data should have arrivedat the destination flip-flop to be stored correctly, including the setup time (uTsu) shown in the last line.From the diagram we see that the time the data arrives at its destination is after the time it is required to arrive if itis to meet the timing constraint. Thus, the timing constraint is violated.
To indicate this, a negative slack value isshown to indicate by how much the timing constraint is violated. In contrast, a timing constraint that is satisfied hasa positive slack value.Altera Corporation - University ProgramJanuary 20119U SING T IME Q UEST T IMING A NALYZERFigure 11. Interpreting setup time information for a given register-to-register path.4.3Setting Up Timing Constraints for a DesignTimeQuest provides a way to specify timing constraints to be included in the next compilation of your design throughthe Constraints menu. To assign a clock constraint, select Create Clock... from the Constraint menu.
A windowshown in Figure 12 will appear.Figure 12. TimeQuest window to create a clock constraint.In the window, the constraint on the clock signal can be specified. To do this give the clock constraint a name (forexample, the name of the clock for which constraints are specified) in the top field. Then, specify the clock periodto be 4ns in the field below.
The next two fields define the time at which the clock changes from 0 to 1 and 1 to 0.10Altera Corporation - University ProgramJanuary 2011U SING T IME Q UEST T IMING A NALYZERLeave these fields empty to indicate that the rising edge of the clock should appear at time 0, and a falling edge atone half of the clock period.
Finally, specify the Targets field to be clock as shown in the figure, to indicate that thegiven constraint is for the clock signal named clock. Then press the Run button to apply the constraint and save theconstraints file into example.sdc file, by double-clicking on the Write SDC File... task as shown in Figure 13.Figure 13. Saving a constraints file.Once the constraints file is saved, it can be used by Quartus II when compiling a project.
This is done by addingthe example.sdc file to the TimeQuest timing analyzer settings as shown in Figure 14. Once the constraint file isadded, recompile the project and open up the setup summary report, as before, in TimeQuest. You will now noticethat the timing constraint is met.5Regarding Designs with Multiple Clock SignalsTimeQuest is capable of analyzing circuits that contain multiple clocks. This includes cases where the designerused several clocks, or clock signals were automatically to support features such as the SignalTap II Logic Analyzeror a JTAG interface. Should the reader work with such designs, it is important to note that the initial experiencewith TimeQuest may differ from that described above.
In designs with multiple clocks, it is important to applyconstraints to each clock before performing timing analysis. Doing so will make the analyzer provide the samereports as described in previous sections.6ConclusionThis tutorial demonstrated the basic use of the TimeQuest timing analyzer. While the descriptions of timing analysisand setting up timing constraints were limited to clock constraints in a simple circuit, TimeQuest provides even morepowerful tools to specify timing constraints for larger and more complex designs.Altera Corporation - University ProgramJanuary 201111U SING T IME Q UEST T IMING A NALYZERFigure 14.
Including a constraints file in Quartus II project.Copyright ©1991-2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, thestylized Altera logo, specific device designations, and all other words and logos that are identified as trademarksand/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in theU.S. and other countries.
All other product or service names are the property of their respective holders. Alteraproducts are protected under numerous U.S. and foreign patents and pending applications, mask work rights, andcopyrights. Altera warrants performance of its semiconductor products to current specifications in accordance withAltera’s standard warranty, but reserves the right to make changes to any products and services at any time withoutnotice. Altera assumes no responsibility or liability arising out of the application or use of any information, product,or service described herein except as expressly agreed to in writing by Altera Corporation.
Altera customers areadvised to obtain the latest version of device specifications before relying on any published information and beforeplacing orders for products or services.This document is being provided on an “as-is” basis and as an accommodation and therefore all warranties, representations or guarantees of any kind (whether express, implied or statutory) including, without limitation, warrantiesof merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed.12Altera Corporation - University ProgramJanuary 2011.
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