11ETD (1086184), страница 26
Текст из файла (страница 26)
Full test loads are applied during all DC electrical tests and AC timing measurements.2. During AC timing measurements, inputs are driven to 0.4 volts and VDD Ð 0.8 volts while timingmeasurements are taken at the 20% and 70% of VDD points.TEST METHODSFigure A-1 Test MethodsMOTOROLAA-4ELECTRICAL CHARACTERISTICSM68HC11 E SERIESTECHNICAL DATATable A-4 Control TimingVDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to THCharacteristicSymbol1.0 MHzMin Maxdc1.01000 ——4.0dc4.0300—Frequency of OperationfoE-Clock PeriodtcycCrystal FrequencyfXTALExternal Oscillator Frequency4 foProcessor Control Setup TimetPCSUtPCSU = 1/4 tcyc + 50 nsReset Input Pulse WidthPWRSTL8To Guarantee External Reset Vector1Minimum Input Time (Can Be Preempted by Internal Reset)Mode Programming Setup TimetMPS2Mode Programming Hold TimetMPH10Interrupt Pulse Width, IRQ Edge-Sensitive ModePWIRQ 1020PWIRQ = tcyc + 20 ns—Wait Recovery Start-up TimetWRSTimer Pulse Width Input Capture Pulse Accumulator InputPWTIM 1020PWTIM = tcyc + 20 ns2.0 MHzMin Maxdc2.0500——8.0dc8.0175—3.0 MHzMin Maxdc3.0333—— 12.0dc 12.0133—Unit—————81210520—————81210353—————tcycnsns4——5204——3534—tcycnsMHznsMHzMHznstcycNOTES:1.
RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for fourclock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt.Refer to SECTION 5 RESETS AND INTERRUPTS for further detail.2. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.Table A-4a Control Timing (MC68L11E9)VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to THCharacteristicFrequency of OperationE-Clock PeriodCrystal FrequencyExternal Oscillator FrequencyProcessor Control Setup TimetPCSU = 1/4 tcyc + 75 nsReset Input Pulse WidthTo Guarantee External Reset VectorMinimum Input Time (Can Be Preempted by Internal Reset)Mode Programming Setup TimeMode Programming Hold TimeInterrupt Pulse Width, IRQ Edge-Sensitive ModePWIRQ = tcyc + 20 nsWait Recovery Start-up TimeTimer Pulse Width, Input Capture Pulse Accumulator InputPWTIM = tcyc + 20 nsSymbol1.0 MHzMinMaxdc1.01000——4.0dc4.0325—2.0 MHzMinMaxdc2.0500——8.0dc8.0200—MHznsMHzMHznstMPStMPHPWIRQ812101020—————81210520—————tcyctcyctcycnsnstWRSPWTIM—10204——5204—tcycnsfotcycfXTAL4 fotPCSUPWRSTLUnitNOTES:1.
RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for fourclock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt.Refer to SECTION 5 RESETS AND INTERRUPTS for further detail.2. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.M68HC11 E SERIESTECHNICAL DATAELECTRICAL CHARACTERISTICSMOTOROLAA-5APA[2:0] 1PA[2:0] 2PA71,3PWTIMPA72,3NOTES:1.
Rising edge sensitive input2. Falling edge sensitive input3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.TIMER INPUTS TIMFigure A-2 Timer InputsAMOTOROLAA-6ELECTRICAL CHARACTERISTICSM68HC11 E SERIESTECHNICAL DATAM68HC11 E SERIESTECHNICAL DATAELECTRICAL CHARACTERISTICSADDRESSMODA, MODBRESETEEXTALVDDFFFE4064 tCYCFFFEFFFEFFFEFFFFNEWPCtPCSUFFFEPWRSTLAFigure A-3 POR External Reset Timing DiagramMOTOROLAA-7FFFEtMPSFFFEFFFEtMPHFFFENEWPCPOR EXT RESET TIMFFFFAMOTOROLAA-8ELECTRICAL CHARACTERISTICSIRQ1PWIRQIRQor XIRQtSTOPDELAY3EADDRESS4STOPADDRSTOPADDR + 1STOPADDR + 1OPCODEResume program with instruction which follows the STOP instruction.ADDRESS5STOP RECOVERY TIMFigure A-4 STOP Recovery Timing DiagramINTERNALCLOCKSSTOPADDRSTOPADDR + 1NOTES:1.
Edge Sensitive IRQ pin (IRQE bit = 1)2. Level sensitive IRQ pin (IRQE bit = 0)3. tSTOPDELAY = 4064 tCYC if DLY bit = 1 or 4 tCYC if DLY = 0.4. XIRQ with X bit in CCR = 1.5. IRQ or (XIRQ with X bit in CCR = 0).STOPADDR + 1STOPADDR + 2SPÉSPÐ7SP Ð 8SP Ð 8FFF2(FFF4)FFF3(FFF5)NEWPCM68HC11 E SERIESTECHNICAL DATAM68HC11 E SERIESTECHNICAL DATAWAITADDRWAITADDR + 1PCLSPNOTE: RESET also causes recovery from WAIT.R/WADDRESSIRQ, XIRQ,OR INTERNALINTERRUPTSESP Ð 2ÉSP Ð 8STACK REGISTERSPCH, YL, YH, XL, XH, A, B, CCRSP Ð 1SP Ð 8SP Ð 8ÉSP Ð 8SP Ð 8tPCSUAWAIT RECOVERY TIMFigure A-5 WAIT Recovery from Interrupt Timing DiagramELECTRICAL CHARACTERISTICSMOTOROLAA-9SP Ð 8tWRSSP Ð 8VECTORADDRVECTORADDR + 1NEWPCAMOTOROLAA-10EtPCSUELECTRICAL CHARACTERISTICSFigure A-6 Interrupt Timing DiagramIRQ 1PWIRQIRQ 2, XIRQ,OR INTERNALINTERRUPTADDRESSDATANEXTOPCODENEXTOP + 1OPCODEÐÐR/WNOTES:1.
Edge sensitive IRQ pin (IRQE bit = 1)2. Level sensitive IRQ pin (IRQE bit = 0)SPPCLSP Ð 1SP Ð 2SP Ð 3SP Ð 4SP Ð 5SP Ð 6SP Ð 7PCHIYLIYHIXLIXHBASP Ð 8CCRSP Ð 8VECTORADDRVECTORADDR + 1ÐÐVECTMSBVECTLSBNEWPCOPCODEINTERRUPT TIMM68HC11 E SERIESTECHNICAL DATATable A-5 Peripheral Port TimingVDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to THCharacteristicSymbolFrequency of Operation (E-Clock Frequency)E-Clock Period1.0 MHzMinMaxfodctcyc1000Peripheral Data Setup TimeMCU Read of Ports A, C, D, and EtPDSUPeripheral Data Hold TimeMCU Read of Ports A, C, D, and EtPDHDelay Time, Peripheral Data WriteMCU Write to Port AMCU Writes to Ports B, C, and DtPWD = 1/4 tcyc + 100 nstPWD2.0 MHzMinMax1.0dc—500100—503.0 MHzUnitMinMax2.0dc3.0MHz—333—ns100—100—ns—50—50—ns——200350——200225——200183nsnsInput Data Setup Time (Port C)tIS60—60—60—nsInput Data Hold Time (Port C)tIH100—100—100—nstDEB—350—225—183nsDelay Time, E Fall to STRBtDEB = 1/4 tcyc + 100 nsSetup Time, STRA Asserted to E Fall (Note 1)tAES0—0—0—nsDelay Time, STRA Asserted to Port C Data OutputValidtPCD—100—100—100nsHold Time, STRA Negated to Port C DatatPCH10—10—10—nsThree-State Hold TimetPCZ—150—150—150nsNOTES:1.
If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed onemore cycle.2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively).3. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.M68HC11 E SERIESTECHNICAL DATAELECTRICAL CHARACTERISTICSMOTOROLAA-11ATable A-5a Peripheral Port Timing (MC68L11E9)VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to THCharacteristicSymbolFrequency of Operation (E-Clock Frequency)E-Clock PeriodPeripheral Data Setup TimeMCU Read of Ports A, C, D, and EPeripheral Data Hold TimeMCU Read of Ports A, C, D, and EDelay Time, Peripheral Data WriteMCU Write to Port AMCU Writes to Ports B, C, and D1.0 MHz2.0 MHzUnitMinMaxMinMaxfodc1.0dc2.0MHztcyc1000—500—ns100—100—ns50—50—ns——250400——250275nsnstIS60—60—nstPDSUtPDHtPWDtPWD = 1/4 tcyc + 150 nsInput Data Setup Time (Port C)tIH100—100—nsDelay Time, E Fall to STRBtDEB = 1/4 tcyc + 150 nstDEB—400—275nsSetup Time, STRA Asserted to E Fall (Note 1)tAES0—0—nsInput Data Hold Time (Port C)ADelay Time, STRA Asserted to Port C Data Output ValidtPCD—100—100nsHold Time, STRA Negated to Port C DatatPCH10—10—nsThree-State Hold TimetPCZ—150—150nsNOTES:1.
If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed onemore cycle.2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively).3. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.MCU READ OF PORTEtPDSUtPDHPORTSA, C*, DtPDSUtPDHPORT E* FOR NON-LATCHED OPERATION OF PORT CE9 PORT RD TIMFigure A-7 Port Read Timing DiagramMOTOROLAA-12ELECTRICAL CHARACTERISTICSM68HC11 E SERIESTECHNICAL DATAMCU WRITE TO PORTEt PWDPORTSB, C, DPREVIOUS PORT DATANEW DATA VALIDtPWDPREVIOUS PORT DATAPORT ANEW DATA VALIDE9 PORT WR TIMFigure A-8 Port Write Timing DiagramASTRA (IN)t IStISPORT C (IN)SIMPLE INPUT STROBE TIMFigure A-9 Simple Input Strobe Timing DiagramMCU WRITE TO PORT BEtPWDPORT BPREVIOUS PORT DATANEW DATA VALIDtDEBSTRB (OUT)SIMPLE OUTPUT STROBE TIMFigure A-10 Simple Output Strobe Timing DiagramM68HC11 E SERIESTECHNICAL DATAELECTRICAL CHARACTERISTICSMOTOROLAA-13READ PORTCL1EtDEB"READY"tDEBSTRB (OUT)tAESSTRA (IN)tIStIHPORT C (IN)NOTES:1.
After reading PIOC with STAF set2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).PORT C INPUT HNDSHK TIMAFigure A-11 Port C Input Handshake Timing DiagramWRITE PORTCL1Et PWDPORT C (OUT)PREVIOUS PORT DATANEW DATA VALIDtDEB"READY"tDEBSTRB (OUT)tAESSTRA (IN)NOTES:1. After reading PIOC with STAF set2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).PORT C OUTPUT HNDSHK TIMFigure A-12 Port C Output Handshake Timing DiagramMOTOROLAA-14ELECTRICAL CHARACTERISTICSM68HC11 E SERIESTECHNICAL DATAREAD PORTCL 1EtPWDPORT C (OUT)(DDR = 1)tDEBtDEB"READY"STRB (OUT)tAESSTRA (IN)t PCDPORT C (OUT)(DDR = 0)OLD DATAtPCHNEW DATA VALIDt PCZa) STRA ACTIVE BEFORE PORTCL WRITEASTRA (IN)tPCHtPCDPORT C (OUT)(DDR = 0)NEW DATA VALIDb) STRA ACTIVE AFTER PORTCL WRITEtPCZNOTES:1.
After reading PIOC with STAF set2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).3-STATE VAR OUTPUT HNDSHK TIMFigure A-13 Three-State Variation of Output Handshake Timing Diagram(STRA Enables Output Buffer)M68HC11 E SERIESTECHNICAL DATAELECTRICAL CHARACTERISTICSMOTOROLAA-15Table A-6 Analog-To-Digital Converter CharacteristicsVDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, 750 kHz ≤E ≤3.0 MHz, unless otherwise notedCharacteristicParameterMinAbsolute2.0 MHz3.0 MHzMaxMaxUnitNumber of Bits Resolved by A/D Converter—8——BitsNon-LinearityMaximum Deviation from the Ideal A/DTransfer Characteristics——±1/2±1LSBZero ErrorDifference Between the Output of an Idealand an Actual for Zero Input Voltage——±1/2±1LSBFull Scale ErrorDifference Between the Output of an Idealand an Actual A/D for Full-Scale InputVoltage——±1/2±1LSBTotal UnadjustedErrorMaximum Sum of Non-Linearity, Zero Error,and Full-Scale Error——±1/2±1 1/2LSBQuantizationErrorUncertainty Because of ConverterResolution——±1/2±1/2LSBAbsoluteAccuracyDifference Between the Actual Input Voltageand the Full-Scale Weighted Equivalentof the Binary Output Code, All ErrorSources Included——±1±2LSBConversionRangeAnalog Input Voltage RangeVRL—VRHVRHVVRHMaximum Analog Reference Voltage(Note 2)VRL—VRLMinimum Analog Reference Voltage(Note 2)VSS -0.1—VRHVRHV∆VRMinimum Difference between VRH and VRL(Note 2)3———VConversion TimeTotal Time to Perform a SingleAnalog-to-Digital Conversion:—32——tcycResolutionAE ClockVDD + 0.1 VDD + 0.1VInternal RC Oscillator——tcyc + 32tcyc + 32µsMonotonicityConversion Result Never Decreases with anIncrease in Input Voltage and has noMissing Codes—Guaranteed———Zero InputReadingConversion Result when Vin = VRL00———HexFull ScaleReadingConversion Result when Vin = VRH——FFFFHexSampleAnalog Input Acquisition Sampling Time:—12——tcycAcquisitionTimeE Clock——1212µsSample/HoldCapacitanceInput Capacitance During Sample PE[7:0]—20 (Typ)——pFInput LeakageInput Leakage on A/D PinsPE[7:0]——400400nAVRL, VRH——1.01.0µAInternal RC OscillatorNOTES:1.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
