ATmega128 (961843), страница 51
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If differential channels are used, the result is presented in two’s complement form.When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it issufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result isread from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared(default), the result is right adjusted.• ADC9:0: ADC Conversion ResultThese bits represent the result from the conversion, as detailed in “ADC ConversionResult” on page 242.2472467M–AVR–11/04JTAG Interface andOn-chip DebugSystemFeatures• JTAG (IEEE std.
1149.1 Compliant) Interface• Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard• Debugger Access to:– All Internal Peripheral Units– Internal and External RAM– The Internal Register File– Program Counter– EEPROM and Flash Memories• Extensive On-chip Debug Support for Break Conditions, Including– AVR Break Instruction– Break on Change of Program Memory Flow– Single Step Break– Program Memory Breakpoints on Single Address or Address Range– Data Memory Breakpoints on Single Address or Address Range• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface• On-chip Debugging Supported by AVR StudioOverviewThe AVR IEEE std. 1149.1 compliant JTAG interface can be used for•Testing PCBs by using the JTAG Boundary-scan capability•Programming the non-volatile memories, Fuses and Lock bits•On-chip debuggingA brief description is given in the following sections.
Detailed descriptions for Programming via the JTAG interface, and using the Boundary-scan Chain can be found in thesections “Programming Via the JTAG Interface” on page 308 and “IEEE 1149.1 (JTAG)Boundary-scan” on page 254, respectively. The On-chip Debug support is consideredbeing private JTAG instructions, and distributed within ATMEL and to selected thirdparty vendors only.Figure 120 shows a block diagram of the JTAG interface and the On-chip Debug system. The TAP Controller is a state machine controlled by the TCK and TMS signals. TheTAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (Shift Register) between the TDI – input and TDO – output.
TheInstruction Register holds JTAG instructions controlling the behavior of a Data Register.The ID-Register, Bypass Register, and the Boundary-scan Chain are the data registersused for board-level testing. The JTAG Programming Interface (actually consisting ofseveral physical and virtual Data Registers) is used for serial programming via the JTAGinterface.
The Internal Scan Chain and Break Point Scan Chain are used for On-chipdebugging only.Test Access Port – TAP248The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology,these pins constitute the Test Access Port –– TAP. These pins are:•TMS: Test mode select. This pin is used for navigating through the TAP-controllerstate machine.•TCK: Test clock. JTAG operation is synchronous to TCK.•TDI: Test Data In.
Serial input data to be shifted in to the Instruction Register or DataRegister (Scan Chains).•TDO: Test Data Out. Serial output data from Instruction Register or Data Register.ATmega1282467M–AVR–11/04ATmega128The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –which is not provided.When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pinsand the TAP controller is in reset.
When programmed and the JTD bit in MCUCSR iscleared, the TAP input signals are internally pulled high and the JTAG is enabled forBoundary-scan and programming. In this case, the TAP output pin (TDO) is left floatingin states where the JTAG TAP controller is not shifting data, and must therefore be connected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-inputof the next device in the scan chain).
The device is shipped with this fuse programmed.For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin ismonitored by the debugger to be able to detect External Reset sources. The debuggercan also pull the RESET pin low to reset the whole system, assuming only open collectors on the Reset line are used in the application.Figure 120. Block DiagramI/O PORT 0DEVICE BOUNDARYBOUNDARY SCAN CHAINTDITDOTCKTMSJTAG PROGRAMMINGINTERFACETAPCONTROLLERAVR CPUBREAKPOINTUNITBYPASSREGISTERPCInstructionFLOW CONTROLUNITDIGITALPERIPHERALUNITSBREAKPOINTSCAN CHAINADDRESSDECODERJTAG / AVR CORECOMMUNICATIONINTERFACEOCD STATUSAND CONTROLAnalog inputsMUXINTERNALSCANCHAINControl & Clock linesIDREGISTERAddressDataANALOGPERIPHERIALUNITSINSTRUCTIONREGISTERFLASHMEMORYI/O PORT n2492467M–AVR–11/04Figure 121.
TAP Controller State Diagram1Test-Logic-Reset00Run-Test/Idle1Select-DR Scan1Select-IR Scan0011Capture-DRCapture-IR000Shift-DR11Exit1-DR00Pause-DR0Pause-IR110Exit2-DRExit2-IR11Update-DRTAP Controller1Exit1-IR010Shift-IR101Update-IR010The TAP controller is a 16-state finite state machine that controls the operation of theBoundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system. Thestate transitions depicted in Figure 121 depend on the signal present on TMS (shownadjacent to each state transition) at the time of the rising edge at TCK.
The initial stateafter a Power-on Reset is Test-Logic-Reset.As a definition in this document, the LSB is shifted in and out first for all Shift Registers.Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:•250At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enterthe Shift Instruction Register – Shift-IR state. While in this state, shift the 4 bits of theJTAG instructions into the JTAG instruction register from the TDI input at the risingedge of TCK. The TMS input must be held low during input of the 3 LSBs in order toremain in the Shift-IR state.
The MSB of the instruction is shifted in when this stateATmega1282467M–AVR–11/04ATmega128is left by setting TMS high. While the instruction is shifted in from the TDI pin, thecaptured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction selects aparticular Data Register as path between TDI and TDO and controls the circuitrysurrounding the selected Data Register.•Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state.
The instructionis latched onto the parallel output from the Shift Register path in the Update-IRstate. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating thestate machine.•At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter theShift Data Register – Shift-DR state. While in this state, upload the selected DataRegister (selected by the present JTAG instruction in the JTAG Instruction Register)from the TDI input at the rising edge of TCK.
In order to remain in the Shift-DR state,the TMS input must be held low during input of all bits except the MSB. The MSB ofthe data is shifted in when this state is left by setting TMS high. While the DataRegister is shifted in from the TDI pin, the parallel inputs to the Data Registercaptured in the Capture-DR state is shifted out on the TDO pin.•Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selectedData Register has a latched parallel-output, the latching takes place in the UpdateDR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigatingthe state machine.As shown in the state diagram, the Run-Test/Idle state need not be entered betweenselecting JTAG instruction and using Data Registers, and some JTAG instructions mayselect certain functions to be performed in the Run-Test/Idle, making it unsuitable as anIdle state.Note:Independent of the initial state of the TAP Controller, the Test-Logic-Reset state canalways be entered by holding TMS high for 5 TCK clock periods.For detailed information on the JTAG specification, refer to the literature listed in “Bibliography” on page 253.Using the Boundaryscan ChainA complete description of the Boundary-scan capabilities are given in the section “IEEE1149.1 (JTAG) Boundary-scan” on page 254.Using the On-chip Debug As shown in Figure 120, the hardware support for On-chip Debugging consists mainly ofSystem• A scan chain on the interface between the internal AVR CPU and the internalperipheral units•Break point unit•Communication interface between the CPU and JTAG systemAll read or modify/write operations needed for implementing the Debugger are done byapplying AVR instructions via the internal AVR CPU Scan Chain.
The CPU sends theresult to an I/O memory mapped location which is part of the communication interfacebetween the CPU and the JTAG system.The Break point Unit implements Break on Change of Program Flow, Single Step Break,two Program Memory Breakpoints, and two combined break points. Together, the fourbreak points can be configured as either:•4 single Program Memory break points•3 Single Program Memory break point + 1 single Data Memory break point•2 single Program Memory break points + 2 single Data Memory break points•2 single Program Memory break points + 1 Program Memory break point with mask(“range break point”)2512467M–AVR–11/04•2 single Program Memory break points + 1 Data Memory break point with mask“range break point”.A debugger, like the AVR Studio®, may however use one or more of these resources forits internal purpose, leaving less flexibility to the end-user.A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 252.The JTAGEN fuse must be programmed to enable the JTAG Test Access Port.
In addition, the OCDEN fuse must be programmed and no Lock bits must be set for the Onchip Debug system to work. As a security feature, the On-chip Debug system is disabledwhen any Lock bits are set. Otherwise, the On-chip Debug system would have provideda back-door into a secured device.The AVR Studio enables the user to fully control execution of programs on an AVRdevice with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVRInstruction Set Simulator.
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