ATmega8 (961837), страница 8
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This mode is identical toPower-down with the exception that the Oscillator is kept running. From Standby mode,the device wakes up in 6 clock cycles.Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep ModesActive Clock DomainsSleepModeOscillatorsclkCPU clkFLASH clkIO clkADC clkASYIdleXADC NoiseReductionWake-up SourcesTWISPM/Main ClockTimer Osc. INT1 Address Timer EEPROMOtherSource Enabled Enabled INT0 Match2Ready ADC I/OXXXX(2)XXXXXXXXX(2)X(3)XXXXX(3)XX(3)XX(3)XPowerDownPowerSaveX(2)Standby(1)Notes:X(2)XXX(2)1. External Crystal or resonator selected as clock source.2. If AS2 bit in ASSR is set.3.
Only level interrupt INT1 and INT0.Minimizing PowerConsumptionThere are several issues to consider when trying to minimize the power consumption inan AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’sfunctions are operating.
All functions not needed should be disabled. In particular, thefollowing modules may need special consideration when trying to achieve the lowestpossible power consumption.Analog-to-Digital Converter(ADC)If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC shouldbe disabled before entering any sleep mode. When the ADC is turned off and on again,the next conversion will be an extended conversion. Refer to “Analog-to-Digital Converter” on page 193 for details on ADC operation.Analog ComparatorWhen entering Idle mode, the Analog Comparator should be disabled if not used.
Whenentering ADC Noise Reduction mode, the Analog Comparator should be disabled. In theother sleep modes, the Analog Comparator is automatically disabled. However, if theAnalog Comparator is set up to use the Internal Voltage Reference as input, the AnalogComparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” onpage 190 for details on how to configure the Analog Comparator.332486O–AVR–10/04Brown-out DetectorIf the Brown-out Detector is not needed in the application, this module should be turnedoff. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in allsleep modes, and hence, always consume power. In the deeper sleep modes, this willcontribute significantly to the total current consumption.
Refer to “Brown-out Detection”on page 38 for details on how to configure the Brown-out Detector.Internal Voltage ReferenceThe Internal Voltage Reference will be enabled when needed by the Brown-out Detector, the Analog Comparator or the ADC. If these modules are disabled as described inthe sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start upbefore the output is used. If the reference is kept on in sleep mode, the output can beused immediately.
Refer to “Internal Voltage Reference” on page 40 for details on thestart-up time.Watchdog TimerIf the Watchdog Timer is not needed in the application, this module should be turned off.If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,always consume power. In the deeper sleep modes, this will contribute significantly tothe total current consumption. Refer to “Watchdog Timer” on page 41 for details on howto configure the Watchdog Timer.Port PinsWhen entering a sleep mode, all port pins should be configured to use minimum power.The most important thing is then to ensure that no pins drive resistive loads.
In sleepmodes where the both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, theinput buffers of the device will be disabled. This ensures that no power is consumed bythe input logic when not needed. In some cases, the input logic is needed for detectingwake-up conditions, and it will then be enabled. Refer to the section “Digital InputEnable and Sleep Modes” on page 53 for details on which pins are enabled.
If the inputbuffer is enabled and the input signal is left floating or have an analog signal level closeto VCC/2, the input buffer will use excessive power.34ATmega8(L)2486O–AVR–10/04ATmega8(L)System Control andResetResetting the AVRDuring Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. If the program never enables an interrupt source, theInterrupt Vectors are not used, and regular program code can be placed at these locations.
This is also the case if the Reset Vector is in the Application section while theInterrupt Vectors are in the boot section or vice versa. The circuit diagram in Figure 14shows the Reset Logic. Table 15 defines the electrical parameters of the reset circuitry.The I/O ports of the AVR are immediately reset to their initial state when a reset sourcegoes active. This does not require any clock source to be running.After all reset sources have gone inactive, a delay counter is invoked, stretching theinternal reset.
This allows the power to reach a stable level before normal operationstarts. The time-out period of the delay counter is defined by the user through theCKSEL Fuses. The different selections for the delay period are presented in “ClockSources” on page 24.Reset SourcesThe ATmega8 has four sources of Reset:•Power-on Reset. The MCU is reset when the supply voltage is below the Power-onReset threshold (VPOT).•External Reset. The MCU is reset when a low level is present on the RESET pin forlonger than the minimum pulse length.•Watchdog Reset. The MCU is reset when the Watchdog Timer period expires andthe Watchdog is enabled.•Brown-out Reset. The MCU is reset when the supply voltage VCC is below theBrown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.352486O–AVR–10/04Figure 14.
Reset LogicDATA BUSPORFBORFEXTRFWDRFMCU Control and StatusRegister (MCUCSR)Brown-OutReset CircuitBODENBODLEVELPull-up ResistorSPIKEFILTERWatchdogOscillatorClockGeneratorCKDelay CountersTIMEOUTCKSEL[3:0]SUT[1:0]Table 15. Reset CharacteristicsSymbolVPOTConditionMinTypMaxUnitsPower-on Reset ThresholdVoltage (rising)(1)1.42.3VPower-on Reset ThresholdVoltage (falling)1.32.3V0.9VCC1.5µsVRSTRESET Pin Threshold VoltagetRSTMinimum pulse width onRESET PinBrown-out Reset ThresholdVoltage(2)BODLEVEL = 12.42.62.9VBOTBODLEVEL = 03.74.04.5Minimum low voltage period forBrown-out DetectionBODLEVEL = 12µstBODBODLEVEL = 02µsVHYSTBrown-out Detector hysteresis130mVNotes:36Parameter0.2V1.
The Power-on Reset will not work unless the supply voltage has been below VPOT(falling).2. VBOT may be below nominal minimum operating voltage for some devices. Fordevices where this is the case, the device is tested down to VCC = VBOT during theproduction test. This guarantees that a Brown-out Reset will occur before VCC dropsto a voltage where correct operation of the microcontroller is no longer guaranteed.The test is performed using BODLEVEL = 1 for ATmega8L and BODLEVEL = 0 forATmega8. BODLEVEL = 1 is not applicable for ATmega8.ATmega8(L)2486O–AVR–10/04ATmega8(L)Power-on ResetA Power-on Reset (POR) pulse is generated by an On-chip detection circuit.
The detection level is defined in Table 15. The POR is activated whenever VCC is below thedetection level. The POR circuit can be used to trigger the Start-up Reset, as well as todetect a failure in supply voltage.A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determineshow long the device is kept in RESET after VCC rise. The RESET signal is activatedagain, without any delay, when VCC decreases below the detection level.Figure 15. MCU Start-up, RESET Tied to VCCVCCRESETVPOTVRSTtTOUTTIME-OUTINTERNALRESETFigure 16. MCU Start-up, RESET Extended ExternallyVCCRESETTIME-OUTVPOTVRSTtTOUTINTERNALRESET372486O–AVR–10/04External ResetAn External Reset is generated by a low level on the RESET pin.
Reset pulses longerthan the minimum pulse width (see Table 15) will generate a reset, even if the clock isnot running. Shorter pulses are not guaranteed to generate a reset. When the appliedsignal reaches the Reset Threshold Voltage – VRST on its positive edge, the delaycounter starts the MCU after the time-out period tTOUT has expired.Figure 17. External Reset During OperationCCBrown-out DetectionATmega8 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCClevel during operation by comparing it to a fixed trigger level.
The trigger level for theBOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed),or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spikefree Brown-out Detection. The hysteresis on the detection level should be interpreted asVBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.The BOD circuit can be enabled/disabled by the fuse BODEN.
When the BOD isenabled (BODEN programmed), and VCC decreases to a value below the trigger level(VBOT- in Figure 18), the Brown-out Reset is immediately activated. When VCC increasesabove the trigger level (VBOT+ in Figure 18), the delay counter starts the MCU after thetime-out period tTOUT has expired.The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger levelfor longer than tBOD given in Table 15.Figure 18. Brown-out Reset During OperationVCCVBOT-VBOT+RESETTIME-OUTtTOUTINTERNALRESET38ATmega8(L)2486O–AVR–10/04ATmega8(L)Watchdog ResetWhen the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration.
On the falling edge of this pulse, the delay timer starts counting the time-out periodtTOUT. Refer to page 41 for details on operation of the Watchdog Timer.Figure 19. Watchdog Reset During OperationCCCKMCU Control and StatusRegister – MCUCSRThe MCU Control and Status Register provides information on which reset sourcecaused an MCU Reset.Bit76543210––––WDRFBORFEXTRFPORFRead/WriteRRRRR/WR/WR/WR/WInitial Value0000MCUCSRSee Bit Description• Bit 7..4 – Res: Reserved BitsThese bits are reserved bits in the ATmega8 and always read as zero.• Bit 3 – WDRF: Watchdog Reset FlagThis bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or bywriting a logic zero to the flag.• Bit 2 – BORF: Brown-out Reset FlagThis bit is set if a Brown-out Reset occurs.
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