ATmega8 (961837), страница 30
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The following code example shows how to flush thereceive buffer.Assembly Code Example(1)USART_Flush:sbis UCSRA, RXCretinr16, UDRrjmp USART_FlushC Code Example(1)void USART_Flush( void ){unsigned char dummy;while ( UCSRA & (1<<RXC) ) dummy = UDR;}Note:1. The example code assumes that the part specific header file is included.Asynchronous DataReceptionThe USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internallygenerated baud rate clock to the incoming asynchronous serial frames at the RxD pin.The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver.
The asynchronous reception operational rangedepends on the accuracy of the internal baud rate clock, the rate of the incomingframes, and the frame size in number of bits.Asynchronous ClockRecoveryThe clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 65 illustrates the sampling process of the start bit of an incoming frame. The samplerate is 16 times the baud rate for Normal mode, and eight times the baud rate for DoubleSpeed mode. The horizontal arrows illustrate the synchronization variation due to thesampling process. Note the larger time variation when using the Double Speed mode144ATmega8(L)2486O–AVR–10/04ATmega8(L)(U2X = 1) of operation. Samples denoted zero are samples done when the RxD line isidle (i.e., no communication activity).Figure 65. Start Bit SamplingRxDIDLESTARTBIT 0Sample(U2X = 0)0012345678910111213141516123Sample(U2X = 1)01234567812When the clock recovery logic detects a high (idle) to low (start) transition on the RxDline, the start bit detection sequence is initiated.
Let sample 1 denote the first zerosample as shown in the figure. The clock recovery logic then uses samples 8, 9 and 10for Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated withsample numbers inside boxes on the figure), to decide if a valid start bit is received. Iftwo or more of these three samples have logical high levels (the majority wins), the startbit is rejected as a noise spike and the Receiver starts looking for the next high to lowtransition.
If however, a valid start bit is detected, the clock recovery logic issynchronized and the data recovery can begin. The synchronization process is repeatedfor each start bit.Asynchronous Data RecoveryWhen the Receiver clock is synchronized to the start bit, the data recovery can begin.The data recovery unit uses a state machine that has 16 states for each bit in Normalmode and eight states for each bit in Double Speed mode. Figure 66 shows the sampling of the data bits and the parity bit. Each of the samples is given a number that isequal to the state of the recovery unit.Figure 66.
Sampling of Data and Parity BitRxDBIT nSample(U2X = 0)123456789101112131415161Sample(U2X = 1)123456781The decision of the logic level of the received bit is taken by doing a majority voting ofthe logic value to the three samples in the center of the received bit. The center samplesare emphasized on the figure by having the sample number inside boxes. The majorityvoting process is done as follows: If two or all three samples have high levels, thereceived bit is registered to be a logic 1. If two or all three samples have low levels, thereceived bit is registered to be a logic 0.
This majority voting process acts as a low passfilter for the incoming signal on the RxD pin. The recovery process is then repeated untila complete frame is received. Including the first stop bit. Note that the Receiver onlyuses the first stop bit of a frame.Figure 67 shows the sampling of the stop bit and the earliest possible beginning of thestart bit of the next frame.1452486O–AVR–10/04Figure 67. Stop Bit Sampling and Next Start Bit SamplingRxDSTOP 1(A)(B)(C)Sample(U2X = 0)123456789100/10/10/1Sample(U2X = 1)1234560/1The same majority voting is done to the stop bit as done for the other bits in the frame. Ifthe stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.A new high to low transition indicating the start bit of a new frame can come right afterthe last of the bits used for majority voting.
For Normal Speed mode, the first low levelsample can be at point marked (A) in Figure 67. For Double Speed mode the first lowlevel must be delayed to (B). (C) marks a stop bit of full length. The early start bit detection influences the operational range of the Receiver.Asynchronous OperationalRangeThe operational range of the Receiver is dependent on the mismatch between thereceived bit rate and the internally generated baud rate. If the Transmitter is sendingframes at too fast or too slow bit rates, or the internally generated baud rate of theReceiver does not have a similar (see Table 53) base frequency, the Receiver will notbe able to synchronize the frames to the start bit.The following equations can be used to calculate the ratio of the incoming data rate andinternal Receiver baud rate.( D + 1 )SR slow = -----------------------------------------S – 1 + D ⋅ S + SF( D + 2 )SR fast = ----------------------------------( D + 1 )S + S MDSum of character size and parity size (D = 5- to 10-bit)SSamples per bit.
S = 16 for Normal Speed mode and S = 8for Double Speed mode.SFFirst sample number used for majority voting. SF = 8 for Normal Speedand SF = 4 for Double Speed mode.SMMiddle sample number used for majority voting. SM = 9 for Normal Speedand SM = 5 for Double Speed mode.Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to theReceiver baud rate. Rfast is the ratio of the fastest incoming data rate that can beaccepted in relation to the Receiver baud rate.Table 53 and Table 54 list the maximum Receiver baud rate error that can be tolerated.Note that Normal Speed mode has higher toleration of baud rate variations.146ATmega8(L)2486O–AVR–10/04ATmega8(L)Table 53.
Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode(U2X = 0)D#(Data+Parity Bit)Rslow(%)Rfast(%)Max TotalError (%)Recommended MaxReceiver Error (%)593,20106,67+6.67/-6.8± 3.0694,12105,79+5.79/-5.88± 2.0794,81105,11+5.11/-5.19± 2.0895,36104,58+4.58/-4.54± 2.0995,81104,14+4.14/-4.19± 1.51096,17103,78+3.78/-3.83± 1.5Table 54. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode(U2X = 1)D#(Data+Parity Bit)Rslow(%)Rfast(%)Max TotalError (%)Recommended MaxReceiver Error (%)594,12105,66+5.66/-5.88± 2.5694,92104,92+4.92/-5.08± 2.0795,52104,35+4.35/-4.48± 1.5896,00103,90+3.90/-4.00± 1.5996,39103,53+3.53/-3.61± 1.51096,70103,23+3.23/-3.30± 1.0The recommendations of the maximum Receiver baud rate error was made under theassumption that the Receiver and Transmitter equally divides the maximum total error.There are two possible sources for the Receivers Baud Rate error.
The Receiver’s system clock (XTAL) will always have some minor instability over the supply voltage rangeand the temperature range. When using a crystal to generate the system clock, this israrely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. The second source for the error is more controllable.The baud rate generator can not always do an exact division of the system frequency toget the baud rate wanted.
In this case an UBRR value that gives an acceptable low errorcan be used if possible.1472486O–AVR–10/04Multi-processorCommunication ModeSetting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART Receiver. Frames that do notcontain address information will be ignored and not put into the receive buffer. Thiseffectively reduces the number of incoming frames that has to be handled by the CPU,in a system with multiple MCUs that communicate via the same serial bus.
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